31:T50c,md` Some of RTL structures describe **control Logic** and some **DataPath** There is no direct way in Verilog or VHDL to express one or another. In ASIC or FPGA both structures are implemented from the **logic gates** and **Flip-Flops** It might be difficult to classify it with 100% certainty. But one should be able to assign some *fuzzy value* to each **structure** or **wire** by analyzing them in context. ## How to classify? |feature|datapath|control logic| |-|-|-| |perform arithmetic operations (+ - *) |+1| | |has regular 2^N width|+1| | |it called bus|+1| | |affects Flip-Flop enable| |+1| |perform logic operations| |+1| |drive MUX select| |+1| |it is part of FSM| |+1| |has 1-bit width| |+1| |used as condition in **if-else** statement| |+1| |signal reduced by comparison operator| |+1| |loops| |+1| ## Detect State Machines Finite State Machines (FSM) can be extracted from control logic blobs. ## Why to classify? * DataPath and Control Logic require diferent visualization. * DataPath requires more directional drawing (Strict Left-to-Right or Top-to-Bottom) * Control Logic has more loops, Forward/Backward chains * Control Logic Diagram * FSM can be rendered as State Diagram * Rendered in the mix DataPath and Control Logic can have distinct shapes, colors, symbols `32:Tc42,render('g', ` module g ( // per node (target / initiator) input clk, input reset_n, input [31:0] t_0_dat, input t_0_req, output t_0_ack, input [31:0] t_1_dat, input t_1_req, output t_1_ack, output [31:0] i_3_dat, output i_3_req, input i_3_ack ); wire [31:0] dat0, dat0_nxt, dat1, dat1_nxt, dat2, dat2_nxt; // per node assign dat0_nxt = t_0_dat; // node:0 is target port assign dat1_nxt = t_1_dat; // node:1 is target port assign dat2_nxt = (dat0 + dat1); // node:2 operator + assign i_3_dat = dat2; // node:3 is initiator port // per edge wire en0; // edge:0 EB1 reg [31:0] dat0_r; always @(posedge clk) if (en0) dat0_r <= dat0_nxt; assign dat0 = dat0_r; wire en1; // edge:1 EB1 reg [31:0] dat1_r; always @(posedge clk) if (en1) dat1_r <= dat1_nxt; assign dat1 = dat1_r; // edge:2 EB1.5 wire en2_0, en2_1, sel2; reg [31:0] dat2_r0, dat2_r1; always @(posedge clk) if (en2_0) dat2_r0 <= dat2_nxt; always @(posedge clk) if (en2_1) dat2_r1 <= dat2_nxt; assign dat2 = sel2 ? dat2_r1 : dat2_r0; g_ctrl uctrl ( .clk(clk), .reset_n(reset_n), .t_0_req(t_0_req), .t_0_ack(t_0_ack), .t_1_req(t_1_req), .t_1_ack(t_1_ack), .i_3_req(i_3_req), .i_3_ack(i_3_ack), .en0(en0), .en1(en1), .en2_0(en2_0), .en2_1(en2_1), .sel2(sel2) ); endmodule // g module g_ctrl ( // per node (target / initiator) input clk, input reset_n, input t_0_req, output t_0_ack, input t_1_req, output t_1_ack, output i_3_req, input i_3_ack, output en0, output en1, output en2_0, output en2_1, output sel2 ); wire req0, ack0, ack0_0, req0_0, req1, ack1, ack1_0, req1_0, req2, ack2, ack2_0, req2_0; // node:t_0 target assign req0 = t_0_req; assign t_0_ack = ack0; // node:t_1 target assign req1 = t_1_req; assign t_1_ack = ack1; // edge:0 EB1 wire ack0m; reg req0m; assign en0 = req0 & ack0; assign ack0 = ~req0m | ack0m; always @(posedge clk or negedge reset_n) if (~reset_n) req0m <= 1'b0; else req0m <= ~ack0 | req0; // edge:0 fork assign req0_0 = req0m; assign ack0m = ack0_0; // edge:1 EB1 wire ack1m; reg req1m; assign en1 = req1 & ack1; assign ack1 = ~req1m | ack1m; always @(posedge clk or negedge reset_n) if (~reset_n) req1m <= 1'b0; else req1m <= ~ack1 | req1; // edge:1 fork assign req1_0 = req1m; assign ack1m = ack1_0; // edge:2 EB1.5 wire ack2m, req2m; eb15_ctrl uctrl_2 ( .t_0_req(req2), .t_0_ack(ack2), .i_0_req(req2m), .i_0_ack(ack2m), .en0(en2_0), .en1(en2_1), .sel(sel2), .clk(clk), .reset_n(reset_n) ); // edge:2 fork assign req2_0 = req2m; assign ack2m = ack2_0; // node:2 join + // join:2, fork:1 assign req2 = req0_0 & req1_0; assign ack0_0 = ack2 & req1_0; assign ack1_0 = ack2 & req0_0; // node:3 initiator assign i_3_req = req2_0; assign ack2_0 = i_3_ack; endmodule // g_ctrl `)33:T6ab,render('g_ctrl', ` module g_ctrl ( // per node (target / initiator) input clk, input reset_n, input t_0_req, output t_0_ack, input t_1_req, output t_1_ack, output i_3_req, input i_3_ack, output en0, output en1, output en2_0, output en2_1, output sel2 ); wire req0, ack0, ack0_0, req0_0, req1, ack1, ack1_0, req1_0, req2, ack2, ack2_0, req2_0; // node:t_0 target assign req0 = t_0_req; assign t_0_ack = ack0; // node:t_1 target assign req1 = t_1_req; assign t_1_ack = ack1; // edge:0 EB1 wire ack0m; reg req0m; assign en0 = req0 & ack0; assign ack0 = ~req0m | ack0m; always @(posedge clk or negedge reset_n) if (~reset_n) req0m <= 1'b0; else req0m <= ~ack0 | req0; // edge:0 fork assign req0_0 = req0m; assign ack0m = ack0_0; // edge:1 EB1 wire ack1m; reg req1m; assign en1 = req1 & ack1; assign ack1 = ~req1m | ack1m; always @(posedge clk or negedge reset_n) if (~reset_n) req1m <= 1'b0; else req1m <= ~ack1 | req1; // edge:1 fork assign req1_0 = req1m; assign ack1m = ack1_0; // edge:2 EB1.5 wire ack2m, req2m; eb15_ctrl uctrl_2 ( .t_0_req(req2), .t_0_ack(ack2), .i_0_req(req2m), .i_0_ack(ack2m), .en0(en2_0), .en1(en2_1), .sel(sel2), .clk(clk), .reset_n(reset_n) ); // edge:2 fork assign req2_0 = req2m; assign ack2m = ack2_0; // node:2 join + // join:2, fork:1 assign req2 = req0_0 & req1_0; assign ack0_0 = ack2 & req1_0; assign ack1_0 = ack2 & req0_0; // node:3 initiator assign i_3_req = req2_0; assign ack2_0 = i_3_ack; endmodule // g_ctrl `)34:T5eb,render('eb15_ctrl', ` module eb15_ctrl #( parameter S0 = 5'b1_0_10_0, parameter S1 = 5'b1_1_01_0, parameter S2 = 5'b0_1_00_0, parameter S3 = 5'b1_1_10_1, parameter S4 = 5'b0_1_00_1 ) ( input t_0_req, output t_0_ack, output i_0_req, input i_0_ack, output en0, en1, sel, input clk, reset_n ); // State machine reg [4:0] state, state_nxt; always @(posedge clk or negedge reset_n) if (~reset_n) state <= S0; else state <= state_nxt; // state d0 d1 t.ack i.req en0 en1 sel // 0 x x 1 0 t.req 0 0 1_0_10_0 // 1 0 x 1 1 0 t.req 0 1_1_01_0 // 2 0 1 0 1 0 0 0 0_1_00_0 // 3 x 0 1 1 t.req 0 1 1_1_10_1 // 4 1 0 0 1 0 0 1 0_1_00_1 always @* casez({state, t_0_req, i_0_ack}) {S0, 2'b1?} : state_nxt = S1; {S1, 2'b01} : state_nxt = S0; {S1, 2'b10} : state_nxt = S2; {S1, 2'b11} : state_nxt = S3; {S2, 2'b?1} : state_nxt = S3; {S3, 2'b01} : state_nxt = S0; {S3, 2'b10} : state_nxt = S4; {S3, 2'b11} : state_nxt = S1; {S4, 2'b?1} : state_nxt = S1; default state_nxt = state; endcase assign t_0_ack = state[4]; assign i_0_req = state[3]; assign en0 = state[2] & t_0_req; assign en1 = state[1] & t_0_req; assign sel = state[0]; endmodule `)35:[] 2f:{"title":"DataPath or Control logic?","cells":[{"id":0,"value":"md`\n# DataPath or Control logic?\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":62,"value":"$31","pinned":false,"hidden":false,"mode":"ojs"},{"id":144,"value":"md`\n## Example\n\nHere is the case when DataPath and Control logic drew on the same schematic sheet but in two distinct regions.\n\n![](https://raw.githubusercontent.com/wavedrom/logidrom/master/img/alu.svg)\n\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":329,"value":"md`\nControl logic rendered as submodule\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":203,"value":"$32","pinned":false,"hidden":false,"mode":"ojs"},{"id":161,"value":"$33","pinned":false,"hidden":false,"mode":"ojs"},{"id":208,"value":"$34","pinned":false,"hidden":false,"mode":"ojs"},{"id":149,"value":"md`\n\n## References\n\n* https://en.wikipedia.org/wiki/Datapath\n* https://en.wikipedia.org/wiki/Control_logic\n* https://github.com/wavedrom/logidrom/issues/32\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":113,"value":"md`## Appendix`","pinned":false,"hidden":false,"mode":"ojs"},{"id":116,"value":"netlistsvg = {\n var ELK = await require('https://nturley.github.io/netlistsvg/elk.bundled.js')\n window.ELK = ELK\n return require('https://nturley.github.io/netlistsvg/built/netlistsvg.bundle.js')\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":118,"value":"YosysJS = require('https://nturley.github.io/yosysjs.js').catch(() => window.YosysJS)","pinned":false,"hidden":false,"mode":"ojs"},{"id":265,"value":"ys = new Promise(function(accept, reject) { YosysJS.create(\"\", accept) })","pinned":false,"hidden":false,"mode":"ojs"},{"id":125,"value":"render = async (top, src) => html`${await netlistsvg.render(netlistsvg.digitalSkin, (src => {\n ys.write_file(top + '.v', src);\n ys.run('design -reset; read_verilog ' + top + '.v; hierarchy -top ' + top +'; proc; opt_clean; write_json output.json');\n return JSON.parse(ys.read_file('output.json'));\n})(src))}`","pinned":false,"hidden":false,"mode":"ojs"}],"files":"$W35","stdlib":"1","titling":"auto"}