30:[] 2e:{"title":"NOP-V","cells":[{"id":0,"value":"# NOP-V\n\nThe RISC-V [User-Level ISA Specification](https://riscv.org/specifications/) defines NOP instruction as:\n\n > The NOP instruction does not change any user-visible state, except for advancing the pc.\n > NOP is encoded as \\`ADDI x0, x0, 0\\`.","pinned":false,"hidden":false,"mode":"md"},{"id":344,"value":"wd(\n\n{reg:[\n {name: 'opcode', bits: 7, attr: 0b0010011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: 0},\n {name: 'rs1', bits: 5, attr: 0},\n {name: 'imm', bits: 12, attr: 0}\n], config: {hspace: width}}\n\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":346,"value":"The spec have the following note:\n\n > NOPs can be used to align code segments to microarchitecturally significant address boundaries,\n > or to leave space for inline code modifications. Although **there are many possible ways** to encode\n > a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well\n > as for more readable disassembly output.\n\nHow many other possible ways to encode NOP?\n\n## rd = 0\n\nAny Integer Computational instruction writing into \\`x0\\` is NOP.","pinned":false,"hidden":false,"mode":"md"},{"id":154,"value":"### RV32I\n\nThese instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9)\n\n`{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ?` ( ${ 6 * 1 << 17} )","pinned":false,"hidden":false,"mode":"md"},{"id":354,"value":"wd(\n{reg: [\n {name: 'OP-IMM', bits: 7, attr: 0b0010011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']},\n {bits: 17}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":356,"value":"`{SLLI, SRLI, SRAI} x0, ?` ( ${ 3 * 1 << 10} )","pinned":false,"hidden":false,"mode":"md"},{"id":379,"value":"wd( \n{reg:[\n {name: 'OP-IMM', bits: 7, attr: 0b0010011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},\n {bits: 10},\n {name: 'imm?', bits: 7, attr: [0, 0, 32]}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":381,"value":"`{LUI, AUIPC} x0, ?` ( ${ 2 * (1 << 20) } )","pinned":false,"hidden":false,"mode":"md"},{"id":383,"value":"wd(\n{reg:[\n {name: 'opcode', bits: 7, attr: ['AUIPC', 'LUI']},\n {name: 'rd', bits: 5, attr: 0},\n {bits: 20}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":385,"value":"`{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ?` ( ${ 10 * 1 << 10} )","pinned":false,"hidden":false,"mode":"md"},{"id":387,"value":"wd(\n{reg:[\n {name: 'OP', bits: 7, attr: 0b0110011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ')},\n {bits: 10},\n {name: 'func7', bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":131,"value":"RV32I = (\n 6 * (1 << 17) +\n 3 * (1 << 10) +\n 2 * (1 << 20) +\n 10 * (1 << 10)\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":111,"value":"### RV64I\n\nThese instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (4.4)\n\nAll RV32I NOPs plus:\n\n`ADDIW x0, ?` ( ${ 1 << 17 } )","pinned":false,"hidden":false,"mode":"md"},{"id":392,"value":"wd(\n{reg:[\n {name: 'OP-IMM-32', bits: 7, attr: 0b0011011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: 'ADDIW'},\n {bits: 17}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":394,"value":"Extra bit for the shift ammont:\n\n`{SLLI, SRLI, SRAI} x0, ?` ( ${ 3 * 1 << 10} )","pinned":false,"hidden":false,"mode":"md"},{"id":396,"value":"wd(\n{reg: [\n {name: 'OP-IMM', bits: 7, attr: 0b0010011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},\n {bits: 10},\n {name: 'imm?', bits: 7, attr: [1, 33, 33]}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":398,"value":"`{SLLIW, SRLIW, SRAIW} x0, ?` ( ${ 3 * 1 << 10} )","pinned":false,"hidden":false,"mode":"md"},{"id":400,"value":"wd(\n{reg:[\n {name: 'OP-IMM-32', bits: 7, attr: 0b0011011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: ['SLLIW', 'SRLIW', 'SRAIW']},\n {bits: 10},\n {name: 'imm?', bits: 7, attr: [0, 32, 32]}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":402,"value":"`SLL, SLT, SRA` ( ??? )\n\n`{ADDW, SLLW, SRLW, SUBW, SRAW} x0, ?, ?` ( ${ 5 * 1 << 10 } )","pinned":false,"hidden":false,"mode":"md"},{"id":404,"value":"wd(\n{reg:[\n {name: 'OP-32', bits: 7, attr: 0b0111011},\n {name: 'rd', bits: 5, attr: 0},\n {name: 'func3', bits: 3, attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']},\n {bits: 10},\n {name: 'func7', bits: 7, attr: [0, 0, 32, 0, 32]}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":145,"value":"RV64I = (\n (1 << 17) +\n 3 * (1 << 10) +\n 2 * (1 << 10) +\n 5 * (1 << 10)\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":152,"value":"md`\n## rd = rs\n\nRead register A (x1..x31), perform computation that preseves the value, and write back to the same register A.\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":157,"value":"### RV32I\n\n`{ADDI, XORI, ORI} A, A, 0` ( ${3 * 31} )","pinned":false,"hidden":false,"mode":"md"},{"id":408,"value":"wd(\n{reg:[\n {name: 'OP-IMM', bits: 7, attr: 0b0010011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: ['ADDI', 'XORI', 'ORI']},\n {name: 'rs1', bits: 5, attr: 'A'},\n {name: 'imm', bits: 12, attr: 0}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":410,"value":"`ANDI A, A, -1` ( 31 )","pinned":false,"hidden":false,"mode":"md"},{"id":412,"value":"wd(\n{reg:[\n {name: 'OP-IMM', bits: 7, attr: 0b0010011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: 'ANDI'},\n {name: 'rs1', bits: 5, attr: 'A'},\n {name: 'imm', bits: 12, attr: -1}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":414,"value":"`{ADD, SUB, OR, XOR, SLL, SRL, SRA} A, A, x0` ( ${ 7 * 31} )","pinned":false,"hidden":false,"mode":"md"},{"id":416,"value":"wd(\n{reg:[\n {name: 'OP', bits: 7, attr: 0b0110011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: 'ADD SUB OR XOR SLL SRL SRA'.split(' ')},\n {name: 'rs1', bits: 5, attr: 'A'},\n {name: 'rs2', bits: 5, attr: 0},\n {name: 'func7', bits: 7, attr: [0, 0, 0, 0, 0, 32, 32]}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":418,"value":"`{ADD, OR, XOR} A, x0, A` ( ${ 3 * 31} )","pinned":false,"hidden":false,"mode":"md"},{"id":420,"value":"wd(\n{reg:[\n {name: 'OP', bits: 7, attr: 0b0110011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: ['ADD', 'OR', 'XOR']},\n {name: 'rs1', bits: 5, attr: 0},\n {name: 'rs2', bits: 5, attr: 'A'},\n {name: 'func7', bits: 7, attr: 0}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":424,"value":"`{AND, OR} A, A, A` ( ${ 2 * 31} )","pinned":false,"hidden":false,"mode":"md"},{"id":426,"value":"wd(\n{reg:[\n {name: 'OP', bits: 7, attr: 0b0110011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: ['AND', 'OR']},\n {name: 'rs1', bits: 5, attr: 'A'},\n {name: 'rs2', bits: 5, attr: 'A'},\n {name: 'func7', bits: 7, attr: 0}\n], config: {hspace: width}\n})","pinned":true,"hidden":false,"mode":"ojs"},{"id":173,"value":"RV32I_extra = (\n 3 * 31 +\n 31 +\n 7 * 31 +\n 3 * 31 +\n 2 * 31\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":175,"value":"### RV64I\n\nAll RV32I NOPs plus:\n\n`{ADDIW, SLLIW, SRLIW, SRAIW} A, A, 0` ( ${ 4 * 31 } )","pinned":false,"hidden":false,"mode":"md"},{"id":431,"value":"wd(\n{reg: [\n {name: 'OP-IMM-32', bits: 7, attr: 0b0011011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: ['ADDIW', 'SLLIW', 'SRLIW', 'SRAIW']},\n {name: 'rs1', bits: 5, attr: 'A'},\n {name: 'imm', bits: 12, attr: 0}\n], config: {hspace: width}\n})","pinned":true,"hidden":false,"mode":"ojs"},{"id":433,"value":"`{ADDW, SUBW, SLLW, SRLW, SRAW} A, A, x0 ` ( ${ 5 * 31} )","pinned":false,"hidden":false,"mode":"md"},{"id":435,"value":"wd(\n{reg: [\n {name: 'OP-32', bits: 7, attr: 0b0011011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: ['ADDW', 'SUBW', 'SLLW', 'SRLW', 'SRAW']},\n {name: 'rs1', bits: 5, attr: 'A'},\n {name: 'rs2', bits: 5, attr: 0},\n {name: 'imm', bits: 7, attr: [0, 0, 0, 32, 32]}\n], config: {hspace: width}}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":437,"value":"`ADDW A, x0, A` ( 31 )","pinned":false,"hidden":false,"mode":"md"},{"id":439,"value":"wd(\n{reg: [\n {name: 'OP', bits: 7, attr: 0b0011011},\n {name: 'rd', bits: 5, attr: 'A'},\n {name: 'func3', bits: 3, attr: 'ADDW'},\n {name: 'rs1', bits: 5, attr: 0},\n {name: 'rs2', bits: 5, attr: 'A'},\n {name: 'func7', bits: 7, attr: 0}\n], config: {hspace: width}\n}\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":184,"value":"RV64I_extra = (\n 4 * 31 +\n 5 * 31 +\n 31\n)","pinned":true,"hidden":false,"mode":"ojs"},{"id":4,"value":"md`\n## Appendix\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":300,"value":"wd = (() => {\n let i = 0;\n return obj => html`${wavedrom.onml.stringify(wavedrom.renderAny(i++, obj, wavedrom.waveSkin))}`\n})()","pinned":false,"hidden":false,"mode":"ojs"},{"id":299,"value":"wavedrom = require('wavedrom@3')","pinned":false,"hidden":false,"mode":"ojs"}],"files":"$W30","stdlib":"1","titling":"auto"}