30:T4aa,md` ## 3.3. Vector type register, vtype ${csr([ {bits: 3, name: 'vlmul', desc: ['div', `Vector Register Grouping`, table(` vlmul | LMUL | #groups | VLMAX | Grouped registers 100 | - | - | - | reserved 101 | 1/8 | 32 | VLEN / SEW / 8 | v n (single register in group) 110 | 1/4 | 32 | VLEN / SEW / 4 | v n (single register in group) 111 | 1/2 | 32 | VLEN / SEW / 2 | v n (single register in group) 000 | 1 | 32 | VLEN / SEW | v n (single register in group) 001 | 2 | 16 | 2 * VLEN/SEW | vn, vn+1 010 | 4 | 8 | 4 * VLEN/SEW | vn, ..., vn+3 011 | 8 | 4 | 8 * VLEN/SEW | vn, ..., vn+7 `) ]}, {bits: 3, name: 'vsew', desc: ['div', 'Standard element width', table(` Value | Width 000 | 8 001 | 16 010 | 32 011 | 64 100 | 128 101 | 256 110 | 512 111 | 1024 `) ]}, {bits: 1, name: 'vta', desc: 'Vector tail agnostic'}, {bits: 1, name: 'vma', desc: 'Vector mask agnostic'}, {bits: 23}, {bits: 1, name: 'vill', desc: 'Illegal value if set'}, ])} `31:T62c,vmem-format.adoc Format for Vector Load Instructions under LOAD-FP major opcode

31 29  28  27 26  25  24      20 19       15 14   12 11      7 6     0
 nf  | mew| mop | vm |  lumop   |    rs1    | width |    vd   |0000111| VL*  unit-stride
 nf  | mew| mop | vm |   rs2    |    rs1    | width |    vd   |0000111| VLS* strided
 nf  | mew| mop | vm |   vs2    |    rs1    | width |    vd   |0000111| VLX* indexed
  3     1    2     1      5           5         3         5       7

${isa([ {bits: 7, name: 0b0000111, attr: 'VL* unit-stride'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 'lumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 7, name: 0b0000111, attr: 'VLS* strided'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 'rs2', attr: 'stride', type: 4}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 7, name: 0b0000111, attr: 'VLX* indexed'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} 32:T60b,md` Format for Vector Store Instructions under STORE-FP major opcode

31 29  28  27 26  25  24      20 19       15 14   12 11      7 6     0
 nf  | mew| mop | vm |  sumop   |    rs1    | width |   vs3   |0100111| VS*  unit-stride
 nf  | mew| mop | vm |   rs2    |    rs1    | width |   vs3   |0100111| VSS* strided
 nf  | mew| mop | vm |   vs2    |    rs1    | width |   vs3   |0100111| VSX* indexed
  3     1    2     1      5           5         3         5        7

${isa([ {bits: 7, name: 0b0100111, attr: 'VS* unit-stride'}, {bits: 5, name: 'vs3', attr: 'store data', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 'sumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 7, name: 0b0100111, attr: 'VSS* strided'}, {bits: 5, name: 'vs3', attr: 'store data', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 'rs2', attr: 'stride', type: 4}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 7, name: 0b0100111, attr: 'VSX* indexed'}, {bits: 5, name: 'vs3', attr: 'store data', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} `33:T9b4,md` valu-format.adoc Formats for Vector Arithmetic Instructions under OP-V major opcode

31       26  25   24      20 19      15 14   12 11      7 6     0
  funct6   | vm  |   vs2    |    vs1   | 0 0 0 |    vd   |1010111| OP-V (OPIVV)
  funct6   | vm  |   vs2    |    vs1   | 0 0 1 |  vd/rd  |1010111| OP-V (OPFVV)
  funct6   | vm  |   vs2    |    vs1   | 0 1 0 |  vd/rd  |1010111| OP-V (OPMVV)
  funct6   | vm  |   vs2    |   simm5  | 0 1 1 |    vd   |1010111| OP-V (OPIVI)
  funct6   | vm  |   vs2    |    rs1   | 1 0 0 |    vd   |1010111| OP-V (OPIVX)
  funct6   | vm  |   vs2    |    rs1   | 1 0 1 |    vd   |1010111| OP-V (OPFVF)
  funct6   | vm  |   vs2    |    rs1   | 1 1 0 |  vd/rd  |1010111| OP-V (OPMVX)
     6        1        5          5        3        5        7

${isa([ {bits: 7, name: 0b1010111, attr: 'OPIVV'}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 0x1000}, {bits: 5, name: 'vs1', type: 2}, {bits: 5, name: 'vs2', type: 2}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPFVV'}, {bits: 5, name: 'vd / rd', type: 7}, {bits: 3, name: 1}, {bits: 5, name: 'vs1', type: 2}, {bits: 5, name: 'vs2', type: 2}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPMVV'}, {bits: 5, name: 'vd / rd', type: 7}, {bits: 3, name: 2}, {bits: 5, name: 'vs1', type: 2}, {bits: 5, name: 'vs2', type: 2}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: ['OPIVI']}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 3}, {bits: 5, name: 'simm5', type: 5}, {bits: 5, name: 'vs2', type: 2}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPIVX'}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 4}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 2}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPFVF'}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 5}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 2}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPMVX'}, {bits: 5, name: 'vd / rd', type: 7}, {bits: 3, name: 6}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 2}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} `34:T52a,md` Format for Vector Load Instructions under LOAD-FP major opcode ### VL* unit-stride ${isa([ {bits: 7, name: 0b0000111, attr: 'VLE*'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 0x10000, attr: 'lumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 0x10000, attr: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 7, name: 0b0000111, attr: 'VLR whole registers'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 8, attr: 'lumop'}, {bits: 1, name: 1, attr: 'vm'}, {bits: 2, name: 0x10000, attr: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 7, name: 0b0000111, attr: 'VLE*FF fault-only-first'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 16, attr: 'lumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 0x1000, attr: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} `35:T53e,md` ## 7.9. Vector Load/Store Whole Register Instructions Format for Vector Load Whole Register Instructions under LOAD-FP major opcode

31 29  28  27 26  25 24   20 19       15 14   12 11      7 6     0
 nf  | mew|  00  | 1| 01000 |    rs1    | width |    vd   |0000111| VLR

${isa([ {bits: 7, name: 0b0000111, attr: 'VLR'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 8, attr: 'lumop'}, {bits: 1, name: 1, attr: 'vm'}, {bits: 2, name: 0x10000, attr: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ])} Format for Vector Store Whole Register Instructions under STORE-FP major opcode
31 29 28 27 26 25 24 20 19 15 14 12 11 7 6 0 nf | 0 | 00 | 1| 01000 | rs1 | 000 | vs3 |0100111| VSR
${isa([ {bits: 7, name: 0b0100111, attr: ['VSR']}, {bits: 5, name: 'vs3', attr: 'store data', type: 2}, {bits: 3, name: 0x1000}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 8, attr: 'sumop'}, {bits: 1, name: 1, attr: 'vm'}, {bits: 2, name: 0x10, attr: 'mop'}, {bits: 1, name: 0x100, attr: 'mew'}, {bits: 3, name: 'nf'}, ])} `36:Ta77,md` # 11. Vector Arithmetic Instruction Formats Formats for Vector Arithmetic Instructions under OP-V major opcode
31 26 25 24 20 19 15 14 12 11 7 6 0 funct6 | vm | vs2 | vs1 | 0 0 0 | vd |1010111| OP-V (OPIVV) funct6 | vm | vs2 | vs1 | 0 0 1 | vd/rd |1010111| OP-V (OPFVV) funct6 | vm | vs2 | vs1 | 0 1 0 | vd/rd |1010111| OP-V (OPMVV) funct6 | vm | vs2 | simm5 | 0 1 1 | vd |1010111| OP-V (OPIVI) funct6 | vm | vs2 | rs1 | 1 0 0 | vd |1010111| OP-V (OPIVX) funct6 | vm | vs2 | rs1 | 1 0 1 | vd |1010111| OP-V (OPFVF) funct6 | vm | vs2 | rs1 | 1 1 0 | vd/rd |1010111| OP-V (OPMVX) 6 1 5 5 3 5 7
${isa([ {bits: 7, name: 0b1010111, attr: 'OPIVV'}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 0x1000}, {bits: 5, name: 'vs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPFVV'}, {bits: 5, name: 'vd / rd', type: 7}, {bits: 3, name: 1}, {bits: 5, name: 'vs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPMVV'}, {bits: 5, name: 'vd / rd', type: 7}, {bits: 3, name: 2}, {bits: 5, name: 'vs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: ['OPIVI']}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 3}, {bits: 5, name: 'simm5', type: 5}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPIVX'}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 4}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPFVF'}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 5}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} ${isa([ {bits: 7, name: 0b1010111, attr: 'OPMVX'}, {bits: 5, name: 'vd / rd', type: 7}, {bits: 3, name: 6}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ])} `37:T525,md` #### Format for Vector Load Instructions under LOAD-FP major opcode ${isa([ {bits: 7, name: 0b0000111, attr: ['VL* unit-stride', 'VLS* strided', 'VLX* indexed']}, {bits: 5, name: 'vd', attr: 'destination of load'}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address'}, {bits: 5, name: 'src2', attr: ['lumop', 'rs2', 'vs2']}, {bits: 1, name: 'vm'}, {bits: 3, name: 'mop'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 20, attr: ['unit-stride', 'unit-stride fault-only-first']}, {bits: 5, name: 'lumop', attr: [0b00000, 0b10000]}, {bits: 7} ])} #### memory addressing mode ${isa([ {bits: 7, attr: [ 'VLxI, VLE', null, 'VLSxU, VLSE', 'VLXxU, VLXE', 'VLx (x != E)', null, 'VLSx (x != E)', 'VLXx (x != E)', ]}, {bits: 5}, {bits: 3}, {bits: 5, attr: [ 'unit-stride', null, 'strided', 'indexed', 'unit-stride', null, 'strided', 'indexed' ]}, {bits: 5, attr: [ 'zero-extended', null, 'zero-extended', 'zero-extended', 'sign-extended', null, 'sign-extended', 'sign-extended' ]}, {bits: 1}, {bits: 3, name: 'mop', attr: [0, 1, 2, 3, 4, 5, 6, 7]}, {bits: 3} ])} `38:T40e,md` #### Format for Vector Store Instructions under STORE-FP major opcode ${isa([ {bits: 7, name: '0100111', attr: ['VS* unit-stride', 'VSS* strided', 'VSX* indexed']}, {bits: 5, name: 'vs3', attr: 'store data'}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address'}, {bits: 5, name: 'src2', attr: ['sumop', 'rs2', 'vs2']}, {bits: 1, name: 'vm'}, {bits: 3, name: 'mop'}, {bits: 3, name: 'nf'}, ])} ${isa([ {bits: 20, attr: 'unit-stride'}, {bits: 5, name: 'sumop', attr: 0}, {bits: 7} ])} #### memory addressing mode ${isa([ {bits: 7, attr: [ 'VSx', null, 'VSSx', 'VSXx', null, null, null, 'VSUXx', ]}, {bits: 5}, {bits: 3}, {bits: 5}, {bits: 5, attr: [ 'unit-stride', null, 'strided', 'indexed-ordered', null, null, null, 'indexed-unordered' ]}, {bits: 1}, {bits: 3, name: 'mop', attr: [0, 1, 2, 3, 4, 5, 6, 7]}, {bits: 3} ])} `39:T793,md` ### Vector Load/Store Width Encoding The vector loads and stores are encoded using the width values that are not claimed by the standard scalar floating-point loads and stores. Three of the width types encode vector loads and stores that move fixed-size memory elements of 8 bits, 16 bits, or 32 bits, while the fourth encoding moves SEW-bit memory elements. ${isa([ {bits: 7, attr: [ 'FLH/FSH', 'FLW/FSW', 'FLD/FSD', 'FLQ/FSQ', 'VxB', 'VxH', 'VxW', 'VxE', ]}, {bits: 5, attr: [ ]}, {bits: 3, name: 'width', attr: [0, 1, 2, 3, 4, 5, 6, 7]}, {bits: 5, attr: [ 'FLEN', 'FLEN', 'FLEN', 'FLEN', 'vl * SEW', 'vl * SEW', 'vl * SEW', 'vl * SEW', ]}, {bits: 5, attr: [ '16', '32', '64', '128', 'vl * 8', 'vl * 16', 'vl * 32', 'vl * SEW', ]}, {bits: 1}, {bits: 3, attr: [ 'Standard scalar FP', 'Standard scalar FP', 'Standard scalar FP', 'Standard scalar FP', 'Vector byte', 'Vector halword', 'Vector word', 'Vector element' ]}, {bits: 3} ])} Fixed-sized vector loads can optionally sign or zero-extend their memory element into the destination register element if the register element is wider than the memory element. A fixed-size vector load raises an illegal instruction exception if the destination register element is narrower than the memory element. The variable-sized load is encoded as if a zero-extended load, with what would be the sign-extended encoding of a variable-sized load currently reserved. Fixed-size vector stores take their operand from the least-significant bits of the register element if the register element if wider than the memory element. Fixed-sized vector stores raise an illegal instruction exception if the memory element is wider than the register element. `3a:[] 2e:{"title":"RISC-V \"V\"","cells":[{"id":0,"value":"md`\n# RISC-V \"V\"\n\nhttps://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc\n\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":221,"value":"$30","pinned":false,"hidden":false,"mode":"ojs"},{"id":841,"value":"md`\n## 3.4. Vector Length Register vl\n\n## 3.5. Vector Byte Length vlenb\n\n## 3.6. Vector Start Index CSR vstart\n\n## 3.7. Vector Fixed-Point Rounding Mode Register vxrm\n\n## 3.8. Vector Fixed-Point Saturation Flag vxsat\n\n## 3.9. Vector Control and Status Register vcsr\n\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":284,"value":"md`\n## 5. Vector Instruction Formats\nThe instructions in the vector extension t under four existing major opcodes (LOAD-FP, STORE-FP, AMO) and\none new major opcode (OP-V).\nVector loads and stores are encoding within the scalar floating-point load and store major opcodes (LOADFP/STORE-FP). The vector load and store encodings repurpose a portion of the standard scalar floating-point\nload/store 12-bit immediate eld to provide further vector instruction encoding, with bit 25 holding the\nstandard vector mask bit (see Mask Encoding).\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":326,"value":"$31","pinned":false,"hidden":false,"mode":"md"},{"id":423,"value":"$32","pinned":false,"hidden":false,"mode":"ojs"},{"id":862,"value":"md`\nvamo-format.adoc\n\nFormat for Vector AMO Instructions under AMO major opcode\n\n
\n31 27 26 25 24 20 19 15 14 12 11 7 6 0\n amoop |wd| vm | vs2 | rs1 | width | vs3/vd |0101111| VAMO*\n 5 1 1 5 5 3 5 7\n
\n\n${isa([\n {bits: 7, name: 0b0101111, attr: 'VAMO*'},\n {bits: 5, name: 'vs3 / vd', attr: 'source / destination', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base', type: 4},\n {bits: 5, name: 'vs2', attr: 'address', type: 2},\n {bits: 1, name: 'vm'},\n {bits: 1, name: 'wd'},\n {bits: 5, name: 'amoop'},\n])}\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":869,"value":"$33","pinned":false,"hidden":false,"mode":"ojs"},{"id":871,"value":"md`\nvcfg-format.adoc\n\nFormats for Vector Configuration Instructions under OP-V major opcode\n\n
\n 31 30 25 24 20 19 15 14 12 11 7 6 0\n 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli\n 1 | 000000 | rs2 | rs1 | 1 1 1 | rd |1010111| vsetvl\n 1 6 5 5 3 5 7\n
\n\n${isa([\n {bits: 7, name: 0b1010111, attr: 'vsetvli'},\n {bits: 5, name: 'rd', type: 4},\n {bits: 3, name: 7},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 11, name: 'zimm[10:0]', type: 5},\n {bits: 1, name: '0'},\n])}\n\n${isa([\n {bits: 7, name: 0b1010111, attr: 'vsetvl'},\n {bits: 5, name: 'rd', type: 4},\n {bits: 3, name: 7},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'rs2', type: 4},\n {bits: 6, name: 0b1000000},\n {bits: 1, name: 1},\n])}\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":888,"value":"md`\n## 7.1. Vector Load/Store Instruction Encoding\n\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":892,"value":"$34","pinned":false,"hidden":false,"mode":"ojs"},{"id":895,"value":"md`\n### VLS* strided\n\n${isa([\n {bits: 7, name: 0b0000111, attr: 'VLSE*'},\n {bits: 5, name: 'vd', attr: 'destination of load', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base address', type: 4},\n {bits: 5, name: 'rs2', attr: 'stride', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 2, attr: 'mop'},\n {bits: 1, name: 'mew'},\n {bits: 3, name: 'nf'},\n])}\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":898,"value":"md`\n\n### VLX* indexed\n\n${isa([\n {bits: 7, name: 0b0000111, attr: 'VLXEI*'},\n {bits: 5, name: 'vd', attr: 'destination of load', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base address', type: 4},\n {bits: 5, name: 'vs2', attr: 'address offsets', type: 2},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 3, attr: 'mop'},\n {bits: 1, name: 'mew'},\n {bits: 3, name: 'nf'},\n])}`","pinned":false,"hidden":false,"mode":"ojs"},{"id":917,"value":"md`\n\nFormat for Vector Store Instructions under STORE-FP major opcode\n\n### VS* unit-stride\n\n${isa([\n {bits: 7, name: 0b0100111, attr: 'VSE*'},\n {bits: 5, name: 'vs3', attr: 'store data', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base address', type: 4},\n {bits: 5, name: 0x1000, attr: 'sumop'},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 0x10, attr: 'mop'},\n {bits: 1, name: 'mew'},\n {bits: 3, name: 'nf'},\n])}\n\n${isa([\n {bits: 7, name: 0b0100111, attr: ['VSR whole registers']},\n {bits: 5, name: 'vs3', attr: 'store data', type: 2},\n {bits: 3, name: 0x1000},\n {bits: 5, name: 'rs1', attr: 'base address', type: 4},\n {bits: 5, name: 8, attr: 'sumop'},\n {bits: 1, name: 1},\n {bits: 2, name: 0x10, attr: 'mop'},\n {bits: 1, name: 0x100},\n {bits: 3, name: 'nf'},\n])}\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":946,"value":"md`\n### VSS* strided\n\n${isa([\n {bits: 7, name: 0b0100111, attr: 'VSS*'},\n {bits: 5, name: 'vs3', attr: 'store data', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base address', type: 4},\n {bits: 5, name: 'rs2', attr: 'stride', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 'mop', attr: 2},\n {bits: 1, name: 'mew'},\n {bits: 3, name: 'nf'},\n])}\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":920,"value":"md`\n### VSX* indexed\n\n${isa([\n {bits: 7, name: 0b0100111, attr: 'VSXEI* ordered'},\n {bits: 5, name: 'vs3', attr: 'store data', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base address', type: 4},\n {bits: 5, name: 'vs2', attr: 'address offsets', type: 2},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 1, attr: 'mop'},\n {bits: 1, name: 'mew'},\n {bits: 3, name: 'nf'},\n])}\n\n${isa([\n {bits: 7, name: 0b0100111, attr: 'VSUXEI* unordered'},\n {bits: 5, name: 'vs3', attr: 'store data', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base address', type: 4},\n {bits: 5, name: 'vs2', attr: 'address offsets', type: 2},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 3, attr: 'mop'},\n {bits: 1, name: 'mew'},\n {bits: 3, name: 'nf'},\n])}\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":771,"value":"$35","pinned":false,"hidden":false,"mode":"ojs"},{"id":323,"value":"md`\n# 8. Vector AMO Operations\n\nFormat for Vector AMO Instructions under AMO major opcode\n\n
\n31 27 26 25 24 20 19 15 14 12 11 7 6 0\n amoop |wd| vm | vs2 | rs1 | width | vs3/vd |0101111| VAMO*\n 5 1 1 5 5 3 5 7\n
\n\n${isa([\n {bits: 7, name: 0b0101111, attr: [\n 'vamoSWAP', 'vamoADD', 'vamoXOR', 'vamoAND', 'vamoOR', 'vamoMIN', 'vamoMAX', 'vamoMINU', 'vamoMAXU'\n ]},\n {bits: 5, name: 'vs3 / vd', attr: 'source / destination', type: 2},\n {bits: 3, name: 'width'},\n {bits: 5, name: 'rs1', attr: 'base', type: 4},\n {bits: 5, name: 'vs2', attr: 'address', type: 2},\n {bits: 1, name: 'vm'},\n {bits: 1, name: 'wd'},\n {bits: 5, name: 'amoop', attr: [1, 0, 4, 12, 8, 16, 20, 24, 28]},\n])}\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":320,"value":"$36","pinned":false,"hidden":false,"mode":"ojs"},{"id":12,"value":"md`\n\n## Vector Loads and Stores\n\nVector loads and stores move values between vector registers and memory. Vector loads and stores are masked and do not raise exceptions on inactive elements. Masked vector loads do not update inactive elements in the destination vector register group. Masked vector stores do not update inactive memory elements.\n\n### Vector Load/Store Instruction Encoding\n\nVector loads and stores are encoding within the scalar floating-point load and store major opcodes (LOAD-FP/STORE-FP). The vector load and store encodings repurpose a portion of the standard scalar floating-point load/store 12-bit immediate field to provide further vector instruction encoding, with bit 25 holding the standard vector mask bit (see Mask Encoding).\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":43,"value":"$37","pinned":false,"hidden":false,"mode":"ojs"},{"id":45,"value":"$38","pinned":false,"hidden":false,"mode":"ojs"},{"id":106,"value":"md`\n\n${isa([\n {bits: 20},\n {bits: 5, name: 'rs2', attr: 'stride'},\n {bits: 7}\n])}\n\n${isa([\n {bits: 20},\n {bits: 5, name: 'vs2', attr: 'address offsets'},\n {bits: 7}\n])}\n\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":112,"value":"$39","pinned":false,"hidden":false,"mode":"ojs"},{"id":144,"value":"md`\n\n## Vector Unit-Stride Instructions\n\n\\`\\`\\`\n # Vector unit-stride loads and stores\n\n # vd destination, rs1 base address, vm is mask encoding (v0.t or )\n vlb.v vd, (rs1), vm # 8b signed\n vlh.v vd, (rs1), vm # 16b signed\n vlw.v vd, (rs1), vm # 32b signed\n\n vlbu.v vd, (rs1), vm # 8b unsigned\n vlhu.v vd, (rs1), vm # 16b unsigned\n vlwu.v vd, (rs1), vm # 32b unsigned\n\n vle.v vd, (rs1), vm # SEW\n\n # vs3 store data, rs1 base address, vm is mask encoding (v0.t or )\n vsb.v vs3, (rs1), vm # 8b store\n vsh.v vs3, (rs1), vm # 16b store\n vsw.v vs3, (rs1), vm # 32b store\n vse.v vs3, (rs1), vm # SEW store\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":168,"value":"a = ({\n foo: {\n '_': 'foo',\n bar: {\n 1: 'foo_bar1',\n 2: 'foo_bar2'\n }\n }\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":194,"value":"a.foo._","pinned":false,"hidden":false,"mode":"ojs"},{"id":4,"value":"md`## Appendix`","pinned":false,"hidden":false,"mode":"ojs"},{"id":10,"value":"isa = (obj, opt) => {\n const options = Object.assign({hspace: width}, opt);\n const ml = ['div',\n {style: 'background-color: white;'},\n wavedrom.renderAny(0, {reg: obj, config: options}, wavedrom.waveSkin)\n ];\n const txt = wavedrom.onml.stringify(ml);\n const el = DOM.element('div:div', {});\n el.innerHTML = txt;\n return el;\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":209,"value":"csrTable = props => {\n const head = ['tr', ['th', 'Bits'], ['th', 'Name'], ['th', 'Description']];\n let lsb = 0;\n const p1 = props.map(row => {\n row.lsb = lsb;\n row.msb = lsb + row.bits - 1;\n lsb += row.bits;\n return row;\n });\n const rows = props.map(row => ['tr', ['td', row.msb + ':' + row.lsb], ['td', row.name || '---'], ['td', row.desc || '---']]);\n return ['table'].concat([head]).concat(rows);\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":205,"value":"csr = (obj, opt) => {\n const options = Object.assign({hspace: ((width - 8) >> 5) << 5, lanes: 1}, opt);\n const ml = ['div',\n {style: 'background-color: white;'}, \n wavedrom.renderAny(0, {reg: obj, config: options}, wavedrom.waveSkin),\n csrTable(obj)\n ];\n const txt = wavedrom.onml.stringify(ml);\n const el = DOM.element('div:div', {});\n el.innerHTML = txt;\n return el;\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":245,"value":"table = rows => {\n rows = (typeof rows === 'string') ? rows.trim().split('\\n') : rows;\n return ['table'].concat(rows.map((row, i) => {\n row = (typeof row === 'string') ? row.trim().split('|') : row;\n return ['tr'].concat(row.map(e => [i ? 'td' : 'th', e.toString()]))\n }));\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":555,"value":"wavedrom = require('wavedrom@3')","pinned":false,"hidden":false,"mode":"ojs"}],"files":"$W3a","stdlib":"1","titling":"auto"}