30:T5af,// Vector Loads and Store // https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc // Vector Unit-Stride Instructions (including segment part) // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions // print_insts(Object.keys(opcodesAll.rvv).filter(e => e.match(/v[ls]e(8|16|32|64).v/))) tabler32((labels, fields) => { [0, 1].map(t => { [0, 5, 6, 7].map((eew, ieew) => { labels.push('V' + (t ? 'S' : 'L') + 'E' + (2 ** (ieew + 3)) + '.V') fields.push( {bits: 7, name: 0x7 + (t << 5)}, {bits: 5, name: 'v' + (t ? 's3' : 'd'), type: t ? 4 : 2}, {bits: 3, name: eew}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 0}, {bits: 1, name: 'vm'}, {bits: 2, name: 0}, {bits: 1, name: 0}, {bits: 3, name: 0}, ); }); }); labels.push('VLM.V', 'VSM.V'); fields.push( {bits: 7, name: 0x7}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 0}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 11}, {bits: 1, name: 1}, {bits: 2, name: 0}, {bits: 1, name: 0}, {bits: 3, name: 0}, {bits: 7, name: 0x27}, {bits: 5, name: 'vs3', type: 4}, {bits: 3, name: 0}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 11}, {bits: 1, name: 1}, {bits: 2, name: 0}, {bits: 1, name: 0}, {bits: 3, name: 0}, ); })31:T534,// Vector Indexed-Unordered Instructions (including segment part) // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions // print_insts(Object.keys(opcodesAll.rvv).filter(e => e.match(/v[ls]uxei\d\d?.v/))) tabler32((labels, fields) => { [0, 1].map(t => { [0, 5, 6, 7].map((eew, ieew) => { labels.push('V' + (t ? 'S' : 'L') + 'UXEI' + (2 ** (ieew + 3)) + '.V') fields.push( {bits: 7, name: 0x7 + (t << 5)}, {bits: 5, name: 'v' + (t ? 's3' : 'd'), type: t ? 4 : 2}, {bits: 3, name: eew}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 2, name: 1}, {bits: 1, name: 0}, {bits: 3, name: 0}, ); }); }); [0, 1].map(t => { [0, 5, 6, 7].map((eew, ieew) => { labels.push('V' + (t ? 'S' : 'L') + 'OXEI' + (2 ** (ieew + 3)) + '.V') fields.push( {bits: 7, name: 0x7 + (t << 5)}, {bits: 5, name: 'v' + (t ? 's3' : 'd'), type: t ? 4 : 2}, {bits: 3, name: eew}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'vs2', type: 4}, {bits: 1, name: 'vm'}, {bits: 2, name: 3}, {bits: 1, name: 0}, {bits: 3, name: 0}, ); }); }); })32:[] 2e:{"title":"RISC-V-V OPCODES","cells":[{"id":0,"value":"# RISC-V-V OPCODES","pinned":false,"hidden":false,"mode":"md"},{"id":447,"value":"# 6. Configuration-Setting Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":255,"value":"// configuration setting\n// https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc\n// print_insts(Object.keys(opcodesAll.rvv).filter(e => e.match(/vset/)))\ntabler32((labels, fields) => {\n labels.push('VSETVLI', 'VSETIVLI', 'VSETVL');\n fields.push(\n {bits: 7, name: 0x57},\n {bits: 5, name: 'rd', type: 2},\n {bits: 3, name: 7},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 11, name: 'zimm[10:0]', type: 5},\n {bits: 1, name: '0'},\n \n {bits: 7, name: 0x57},\n {bits: 5, name: 'rd', type: 2},\n {bits: 3, name: 7},\n {bits: 5, name: 'uimm[4:0]', type: 5},\n {bits: 10, name: 'zimm[9:0]', type: 5},\n {bits: 1, name: '1'},\n {bits: 1, name: '1'},\n \n {bits: 7, name: 0x57},\n {bits: 5, name: 'rd', type: 2},\n {bits: 3, name: 7},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'rs2', type: 4},\n {bits: 6, name: 0x1000},\n {bits: 1, name: 1}\n );\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":439,"value":"# 7. Vector Loads and Stores","pinned":false,"hidden":false,"mode":"md"},{"id":456,"value":"## 7.4. Vector Unit-Stride Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":22,"value":"$30","pinned":false,"hidden":false,"mode":"ojs"},{"id":461,"value":"## 7.5. Vector Strided Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":62,"value":"// Vector Strided Instructions (including segment part)\n// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions\n// print_insts(Object.keys(opcodesAll.rvv).filter(e => e.match(/v[ls]se\\d\\d?.v/)))\ntabler32((labels, fields) => {\n [0, 1].map(t => {\n [0, 5, 6, 7].map((eew, ieew) => {\n labels.push('V' + (t ? 'S' : 'L') + 'SE' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x7 + (t << 5)},\n {bits: 5, name: 'v' + (t ? 's3' : 'd'), type: t ? 4 : 2},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'rs2', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 2},\n {bits: 1, name: 0},\n {bits: 3, name: 0},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":468,"value":"## 7.6. Vector Indexed Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":44,"value":"$31","pinned":false,"hidden":false,"mode":"ojs"},{"id":477,"value":"## 7.7. Unit-stride Fault-Only-First Loads","pinned":false,"hidden":false,"mode":"md"},{"id":73,"value":"// Unit-stride F31..29=0ault-Only-First Loads\n// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads\n// print_insts(Object.keys(opcodesAll.rvv).filter(e => e.match(/vle\\d\\d?ff.v/)))\ntabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n labels.push('VLE' + (2 ** (ieew + 3)) + 'FF.V')\n fields.push(\n {bits: 7, name: 0x7},\n {bits: 5, name: 'vd', type: 2},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 16},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 0},\n {bits: 1, name: 0},\n {bits: 3, name: 0},\n );\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":490,"value":"## 7.8. Vector Load/Store Segment Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":494,"value":"### 7.8.1. Vector Unit-Stride Segment Loads and Stores","pinned":false,"hidden":false,"mode":"md"},{"id":325,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VLSEG' + (nf + 2) + 'E' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x7},\n {bits: 5, name: 'vd', type: 2},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 0},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 0},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":336,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VSSEG' + (nf + 2) + 'E' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x27},\n {bits: 5, name: 'vs3', type: 4},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 0},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 0},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":498,"value":"### 7.8.2. Vector Strided Segment Loads and Stores","pinned":false,"hidden":false,"mode":"md"},{"id":352,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VLSSEG' + (nf + 2) + 'EI' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x7},\n {bits: 5, name: 'vd', type: 2},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'rs2', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 2},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":355,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VSSSEG' + (nf + 2) + 'EI' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x27},\n {bits: 5, name: 'vs3', type: 4},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'rs2', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 2},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":502,"value":"### 7.8.3. Vector Indexed Segment Loads and Stores","pinned":false,"hidden":false,"mode":"md"},{"id":343,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VLUXSEG' + (nf + 2) + 'EI' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x7},\n {bits: 5, name: 'vd', type: 2},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'vs2', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 1},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":349,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VSUXSEG' + (nf + 2) + 'EI' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x27},\n {bits: 5, name: 'vs3', type: 4},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'vs2', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 1},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":362,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VLOXSEG' + (nf + 2) + 'EI' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x7},\n {bits: 5, name: 'vd', type: 2},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'vs2', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 3},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":366,"value":"tabler32((labels, fields) => {\n [0, 5, 6, 7].map((eew, ieew) => {\n _.range(7).map(nf => {\n labels.push('VSOXSEG' + (nf + 2) + 'EI' + (2 ** (ieew + 3)) + '.V')\n fields.push(\n {bits: 7, name: 0x27},\n {bits: 5, name: 'vs3', type: 4},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 'vs2', type: 4},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 3},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":369,"value":"tabler32((labels, fields) => {\n [0, 1, 2, 3].map(eew => {\n _.range(7).map(nf => {\n labels.push('VLSEG' + (nf + 2) + 'E' + (2 ** (eew + 3)) + 'FF.V')\n fields.push(\n {bits: 7, name: 0x7},\n {bits: 5, name: 'vd', type: 2},\n {bits: 3, name: eew},\n {bits: 5, name: 'rs1', type: 4},\n {bits: 5, name: 16},\n {bits: 1, name: 'vm'},\n {bits: 2, name: 0},\n {bits: 1, name: 0},\n {bits: 3, name: nf + 1},\n );\n });\n });\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":506,"value":"## 7.9. Vector Load/Store Whole Register Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":76,"value":"// Vector Load/Store Whole Registers\n// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions\nprint_insts(Object.keys(opcodesAll.rvv).filter(e => e.match(/vl(\\d+)re(\\d+).v/) || e.match(/vs(\\d+)r.v/)))","pinned":false,"hidden":false,"mode":"ojs"},{"id":672,"value":"# 11. Vector Integer Arithmetic Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":678,"value":"## 11.1. Vector Single-Width Integer Add and Subtract","pinned":false,"hidden":false,"mode":"md"},{"id":676,"value":"print_insts(`\nvadd.vv vadd.vx vadd.vi\nvsub.vv vsub.vx\nvrsub.vx vrsub.vi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":683,"value":"## 11.2. Vector Widening Integer Add/Subtract","pinned":false,"hidden":false,"mode":"md"},{"id":687,"value":"print_insts(`\nvwaddu.vv vwaddu.vx vwsubu.vv vwsubu.vx\nvwadd.vv vwadd.vx vwsub.vv vwsub.vx\nvwaddu.wv vwaddu.wx vwsubu.wv vwsubu.wx\nvwadd.wv vwadd.wx vwsub.wv vwsub.wx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":692,"value":"## 11.3. Vector Integer Extension","pinned":false,"hidden":false,"mode":"md"},{"id":156,"value":"print_insts(`\nvzext.vf2 vsext.vf2\nvzext.vf4 vsext.vf4\nvzext.vf8 vsext.vf8\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":700,"value":"## 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":696,"value":"print_insts(`\nvadc.vvm vadc.vxm vadc.vim\nvmadc.vvm vmadc.vxm vmadc.vim\n\nvsbc.vvm vsbc.vxm\n\nvmsbc.vvm\nvmsbc.vxm\n\n`)\n/*\nvmadc.vv\nvmadc.vx\nvmadc.vi\n\nvmsbc.vv\nvmsbc.vx\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":719,"value":"## 11.5. Vector Bitwise Logical Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":723,"value":"print_insts(`\nvand.vv vand.vx vand.vi\nvor.vv vor.vx vor.vi\nvxor.vv vxor.vx vxor.vi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":727,"value":"## 11.6. Vector Single-Width Bit Shift Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":733,"value":"print_insts(`\nvsll.vv vsll.vx vsll.vi\nvsrl.vv vsrl.vx vsrl.vi\nvsra.vv vsra.vx vsra.vi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":737,"value":"## 11.7. Vector Narrowing Integer Right Shift Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":741,"value":"print_insts(`\nvnsrl.wv vnsrl.wx vnsrl.wi\nvnsra.wv vnsra.wx vnsra.wi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":745,"value":"## 11.8. Vector Integer Comparison Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":749,"value":"print_insts(`\nvmseq.vv vmseq.vx vmseq.vi\nvmsne.vv vmsne.vx vmsne.vi\nvmsltu.vv vmsltu.vx\nvmslt.vv vmslt.vx\nvmsleu.vv vmsleu.vx vmsleu.vi\nvmsle.vv vmsle.vx vmsle.vi\nvmsgtu.vx vmsgtu.vi\nvmsgt.vx vmsgt.vi\n`)\n/*\nvmsgeu.vx \nvmsge.vx\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":761,"value":"## 11.9. Vector Integer Min/Max Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":765,"value":"print_insts(`\nvminu.vv vminu.vx\nvmin.vv vmin.vx\nvmaxu.vv vmaxu.vx\nvmax.vv vmax.vx\n`)\n/*\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":768,"value":"## 11.10. Vector Single-Width Integer Multiply Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":772,"value":"print_insts(`\nvmul.vv vmul.vx\nvmulh.vv vmulh.vx\nvmulhu.vv vmulhu.vx\nvmulhsu.vv vmulhsu.vx\n`)\n/*\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":774,"value":"## 11.11. Vector Integer Divide Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":779,"value":"print_insts(`\nvdivu.vv vdivu.vx\nvdiv.vv vdiv.vx\nvremu.vv vremu.vx\nvrem.vv vrem.vx\n`)\n/*\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":782,"value":"## 11.12. Vector Widening Integer Multiply Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":787,"value":"print_insts(`\nvwmul.vv vwmul.vx\nvwmulu.vv vwmulu.vx\nvwmulsu.vv vwmulsu.vx\n`)\n/*\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":790,"value":"## 11.13. Vector Single-Width Integer Multiply-Add Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":794,"value":"print_insts(`\nvmacc.vv vmacc.vx\nvnmsac.vv vnmsac.vx\nvmadd.vv vmadd.vx\nvnmsub.vv vnmsub.vx\n`)\n/*\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":796,"value":"## 11.14. Vector Widening Integer Multiply-Add Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":801,"value":"print_insts(`\nvwmaccu.vv vwmaccu.vx\nvwmacc.vv vwmacc.vx\nvwmaccsu.vv vwmaccsu.vx\nvwmaccus.vx\n`)\n/*\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":803,"value":"## 11.15. Vector Integer Merge Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":809,"value":"print_insts(`vmerge.vvm vmerge.vxm vmerge.vim`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":813,"value":"## 11.16. Vector Integer Move Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":817,"value":"print_insts(`vmv.v.v vmv.v.x vmv.v.i`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":819,"value":"# 12. Vector Fixed-Point Arithmetic Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":823,"value":"## 12.1. Vector Single-Width Saturating Add and Subtract","pinned":false,"hidden":false,"mode":"md"},{"id":829,"value":"print_insts(`\nvsaddu.vv vsaddu.vx vsaddu.vi\nvsadd.vv vsadd.vx vsadd.vi\nvssubu.vv vssubu.vx\nvssub.vv vssub.vx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":831,"value":"## 12.2. Vector Single-Width Averaging Add and Subtract","pinned":false,"hidden":false,"mode":"md"},{"id":836,"value":"print_insts(`\nvaaddu.vv vaaddu.vx\nvaadd.vv vaadd.vx\nvasubu.vv vasubu.vx\nvasub.vv vasub.vx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":839,"value":"## 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation","pinned":false,"hidden":false,"mode":"md"},{"id":843,"value":"print_insts(`vsmul.vv vsmul.vx`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":846,"value":"## 12.4. Vector Single-Width Scaling Shift Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":851,"value":"print_insts(`\nvssrl.vv vssrl.vx vssrl.vi\nvssra.vv vssra.vx vssra.vi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":853,"value":"## 12.5. Vector Narrowing Fixed-Point Clip Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":857,"value":"print_insts(`\nvnclipu.wv vnclipu.wx vnclipu.wi\nvnclip.wv vnclip.wx vnclip.wi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":861,"value":"# 13. Vector Floating-Point Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":865,"value":"## 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":870,"value":"print_insts(`\nvfadd.vv vfadd.vf\nvfsub.vv vfsub.vf vfrsub.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":872,"value":"## 13.3. Vector Widening Floating-Point Add/Subtract Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":877,"value":"print_insts(`\nvfwadd.vv vfwadd.vf vfwsub.vv vfwsub.vf\nvfwadd.wv vfwadd.wf vfwsub.wv vfwsub.wf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":880,"value":"## 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":884,"value":"print_insts(`\nvfmul.vv vfmul.vf\nvfdiv.vv vfdiv.vf\nvfrdiv.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":888,"value":"## 13.5. Vector Widening Floating-Point Multiply","pinned":false,"hidden":false,"mode":"md"},{"id":892,"value":"print_insts(`vfwmul.vv vfwmul.vf`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":897,"value":"## 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":901,"value":"print_insts(`\nvfmacc.vv vfmacc.vf\nvfnmacc.vv vfnmacc.vf\nvfmsac.vv vfmsac.vf\nvfnmsac.vv vfnmsac.vf\nvfmadd.vv vfmadd.vf\nvfnmadd.vv vfnmadd.vf\nvfmsub.vv vfmsub.vf\nvfnmsub.vv vfnmsub.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":905,"value":"## 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":909,"value":"print_insts(`\nvfwmacc.vv vfwmacc.vf\nvfwnmacc.vv vfwnmacc.vf\nvfwmsac.vv vfwmsac.vf\nvfwnmsac.vv vfwnmsac.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":911,"value":"## 13.8. Vector Floating-Point Square-Root Instruction\n## 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction\n## 13.10. Vector Floating-Point Reciprocal Estimate Instruction","pinned":false,"hidden":false,"mode":"md"},{"id":915,"value":"print_insts(`\nvfsqrt.v\nvfrsqrt7.v\nvfrec7.v\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":922,"value":"## 13.11. Vector Floating-Point MIN/MAX Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":926,"value":"print_insts(`\nvfmin.vv vfmin.vf\nvfmax.vv vfmax.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":929,"value":"## 13.12. Vector Floating-Point Sign-Injection Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":933,"value":"print_insts(`\nvfsgnj.vv vfsgnj.vf\nvfsgnjn.vv vfsgnjn.vf\nvfsgnjx.vv vfsgnjx.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":937,"value":"## 13.13. Vector Floating-Point Compare Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":941,"value":"print_insts(`\nvmfeq.vv vmfeq.vf\nvmfne.vv vmfne.vf\nvmflt.vv vmflt.vf\nvmfle.vv vmfle.vf\nvmfgt.vf\nvmfge.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":944,"value":"## 13.14. Vector Floating-Point Classify Instruction\n## 13.15. Vector Floating-Point Merge Instruction\n## 13.16. Vector Floating-Point Move Instruction\n","pinned":false,"hidden":false,"mode":"md"},{"id":950,"value":"print_insts(`\nvfclass.v\nvfmerge.vfm\nvfmv.v.f\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":955,"value":"## 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":959,"value":"print_insts(`\nvfcvt.xu.f.v vfcvt.x.f.v\nvfcvt.rtz.xu.f.v vfcvt.rtz.x.f.v\nvfcvt.f.xu.v vfcvt.f.x.v\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":962,"value":"## 13.18. Widening Floating-Point/Integer Type-Convert Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":968,"value":"print_insts(`\nvfwcvt.xu.f.v vfwcvt.x.f.v\nvfwcvt.rtz.xu.f.v vfwcvt.rtz.x.f.v\nvfwcvt.f.xu.v vfwcvt.f.x.v\nvfwcvt.f.f.v\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":971,"value":"## 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":975,"value":"print_insts(`\nvfncvt.xu.f.w vfncvt.x.f.w\nvfncvt.rtz.xu.f.w vfncvt.rtz.x.f.w\nvfncvt.f.xu.w vfncvt.f.x.w\nvfncvt.f.f.w vfncvt.rod.f.f.w\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":977,"value":"# 14. Vector Reduction Operations","pinned":false,"hidden":false,"mode":"md"},{"id":984,"value":"## 14.1. Vector Single-Width Integer Reduction Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":982,"value":"print_insts(`\nvredsum.vs\nvredmaxu.vs\nvredmax.vs\nvredminu.vs\nvredmin.vs\nvredand.vs\nvredor.vs\nvredxor.vs\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":989,"value":"## 14.2. Vector Widening Integer Reduction Instructions\n## 14.3. Vector Single-Width Floating-Point Reduction Instructions\n## 14.4. Vector Widening Floating-Point Reduction Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":994,"value":"print_insts(`\nvwredsumu.vs vwredsum.vs\n\nvfredosum.vs\n\nvfredmax.vs\nvfredmin.vs\n\nvfwredosum.vs\n`)\n/*\n--\nvfredusum.vs\n\n--\nvfwredusum.vs\n\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":1009,"value":"# 15. Vector Mask Instructions\n## 15.1. Vector Mask-Register Logical Instructions\n## 15.2. Vector count population in mask vcpop.m\n## 15.3. vfirst find-first-set mask bit\n## 15.4. vmsbf.m set-before-first mask bit\n## 15.5. vmsif.m set-including-first mask bit\n## 15.6. vmsof.m set-only-first mask bit\n## 15.8. Vector Iota Instruction\n## 15.9. Vector Element Index Instruction","pinned":false,"hidden":false,"mode":"md"},{"id":1014,"value":"print_insts(`\nvmand.mm\nvmnand.mm\nvmandnot.mm\nvmxor.mm\nvmor.mm\nvmnor.mm\nvmornot.mm\nvmxnor.mm\n\nvfirst.m\nvmsbf.m\nvmsif.m\nvmsof.m\nviota.m\nvid.v\n`)\n/*\nvmmv.m\nvmclr.m\nvmset.m\nvmnot.m\n\nvcpop.m\n\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":1038,"value":"# 16. Vector Permutation Instructions\n## 16.1. Integer Scalar Move Instructions\n## 16.2. Floating-Point Scalar Move Instructions\n## 16.3. Vector Slide Instructions\n## 16.4. Vector Register Gather Instructions\n## 16.5. Vector Compress Instruction\n## 16.6. Whole Vector Register Move","pinned":false,"hidden":false,"mode":"md"},{"id":1043,"value":"print_insts(`\nvmv.x.s vmv.s.x\nvfmv.f.s vfmv.s.f\n\nvslideup.vx vslideup.vi\nvslidedown.vx vslidedown.vi\nvslide1up.vx vfslide1up.vf\n\nvslide1down.vx vfslide1down.vf\n\nvrgather.vv vrgatherei16.vv\nvrgather.vx vrgather.vi\n\nvcompress.vm\n\nvmv1r.v vmv2r.v vmv4r.v vmv8r.v\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":706,"value":"----\n\n# Sorted per Instruction format\n\n----","pinned":false,"hidden":false,"mode":"md"},{"id":110,"value":"OPIVV","pinned":false,"hidden":false,"mode":"md"},{"id":114,"value":"print_insts(`\nvadd.vv\nvsub.vv\nvminu.vv\nvmin.vv\nvmaxu.vv\nvmax.vv\nvand.vv\nvor.vv\nvxor.vv\nvrgather.vv\nvrgatherei16.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":116,"value":"print_insts(`\nvadc.vvm\nvmadc.vvm\nvsbc.vvm\nvmsbc.vvm\nvmerge.vvm\nvmv.v.v\nvmseq.vv\nvmsne.vv\nvmsltu.vv\nvmslt.vv\nvmsleu.vv\nvmsle.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":118,"value":"print_insts(`\nvsaddu.vv\nvsadd.vv\nvssubu.vv\nvssub.vv\nvsll.vv\nvsmul.vv\nvsrl.vv\nvsra.vv\nvssrl.vv\nvssra.vv\nvnsrl.wv\nvnsra.wv\nvnclipu.wv\nvnclip.wv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":120,"value":"print_insts(`\nvwredsumu.vs\nvwredsum.vs\nvdotu.vv\nvdot.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":122,"value":"print_insts(`\nvqmaccu.vv\nvqmacc.vv\nvqmaccsu.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":124,"value":"OPIVI","pinned":false,"hidden":false,"mode":"md"},{"id":143,"value":"print_insts(`\nvadd.vi\nvrsub.vi\nvand.vi\nvor.vi\nvxor.vi\nvrgather.vi\nvslideup.vi\nvslidedown.vi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":145,"value":"print_insts(`\nvadc.vim\nvmadc.vim\nvmerge.vim\nvmv.v.i\nvmseq.vi\nvmsne.vi\nvmsleu.vi\nvmsle.vi\nvmsgtu.vi\nvmsgt.vi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":148,"value":"print_insts(`\nvsaddu.vi\nvsadd.vi\nvsll.vi\nvmv1r.v\nvmv2r.v\nvmv4r.v\nvmv8r.v\nvsrl.vi\nvsra.vi\nvssrl.vi\nvssra.vi\nvnsrl.wi\nvnsra.wi\nvnclipu.wi\nvnclip.wi\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":127,"value":"OPMVV","pinned":false,"hidden":false,"mode":"md"},{"id":150,"value":"print_insts(`\nvredsum.vs\nvredand.vs\nvredor.vs\nvredxor.vs\nvredminu.vs\nvredmin.vs\nvredmaxu.vs\nvredmax.vs\nvaaddu.vv\nvaadd.vv\nvasubu.vv\nvasub.vv\n\nvmv.x.s\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":158,"value":"print_insts(`\nvcompress.vm\nvmandnot.mm\nvmand.mm\nvmor.mm\nvmxor.mm\nvmornot.mm\nvmnand.mm\nvmnor.mm\nvmxnor.mm\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":160,"value":"print_insts(`\nvmsbf.m\nvmsof.m\nvmsif.m\nviota.m\nvid.v\nvpopc.m\nvfirst.m\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":162,"value":"print_insts(`\nvdivu.vv\nvdiv.vv\nvremu.vv\nvrem.vv\nvmulhu.vv\nvmul.vv\nvmulhsu.vv\nvmulh.vv\nvmadd.vv\nvnmsub.vv\nvmacc.vv\nvnmsac.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":98,"value":"print_insts(`\nvfwadd.vv\nvfwredsum.vs\nvfwsub.vv\nvfwredosum.vs\nvfwadd.wv\nvfwsub.wv\nvfwmul.vv\nvfdot.vv\nvfwmacc.vv\nvfwnmacc.vv\nvfwmsac.vv\nvfwnmsac.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":164,"value":"print_insts(`\nvwaddu.vv\nvwadd.vv\nvwsubu.vv\nvwsub.vv\nvwaddu.wv\nvwadd.wv\nvwsubu.wv\nvwsub.wv\nvwmulu.vv\nvwmulsu.vv\nvwmul.vv\nvwmaccu.vv\nvwmacc.vv\nvwmaccsu.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":136,"value":"OPMVX","pinned":false,"hidden":false,"mode":"md"},{"id":167,"value":"print_insts(`\nvaaddu.vx\nvaadd.vx\nvasubu.vx\nvasub.vx\n\nvmv.s.x\nvslide1up.vx\nvslide1down.vx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":171,"value":"print_insts(`\nvdivu.vx\nvdiv.vx\nvremu.vx\nvrem.vx\nvmulhu.vx\nvmul.vx\nvmulhsu.vx\nvmulh.vx\nvmadd.vx\nvnmsub.vx\nvmacc.vx\nvnmsac.vx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":173,"value":"print_insts(`\nvwaddu.vx\nvwadd.vx\nvwsubu.vx\nvwsub.vx\nvwaddu.wx\nvwadd.wx\nvwsubu.wx\nvwsub.wx\nvwmulu.vx\nvwmulsu.vx\nvwmul.vx\nvwmaccu.vx\nvwmacc.vx\nvwmaccus.vx\nvwmaccsu.vx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":620,"value":"print_insts(`\nvsaddu.vx vsadd.vx\nvssubu.vx vssub.vx\nvsll.vx\nvsmul.vx\nvsrl.vx vsra.vx\nvssrl.vx vssra.vx\nvnsrl.wx vnsra.wx\nvnclipu.wx vnclip.wx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":564,"value":"# 14. Vector Floating-Point Instructions","pinned":false,"hidden":false,"mode":"md"},{"id":82,"value":"// Vector Floating-Point Instructions\n// https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions\nprint_insts(`\nvfadd.vf\nvfsub.vf\nvfmin.vf\nvfmax.vf\nvfsgnj.vf\nvfsgnjn.vf\nvfsgnjx.vf\nvfslide1up.vf\nvfslide1down.vf\nvfmv.s.f\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":569,"value":"print_insts(`\nvfdiv.vv\nvfmul.vv\nvfmadd.vv\nvfnmadd.vv\nvfmsub.vv\nvfnmsub.vv\nvfmacc.vv\nvfnmacc.vv\nvfmsac.vv\nvfnmsac.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":573,"value":"print_insts(`\nvfmerge.vfm\nvfmv.v.f\nvmfeq.vf\nvmfle.vf\nvmflt.vf\nvmfne.vf\nvmfgt.vf\nvmfge.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":86,"value":"print_insts(`\nvfdiv.vf\nvfrdiv.vf\nvfmul.vf\nvfrsub.vf\nvfmadd.vf\nvfnmadd.vf\nvfmsub.vf\nvfnmsub.vf\nvfmacc.vf\nvfnmacc.vf\nvfmsac.vf\nvfnmsac.vf\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":139,"value":"OPFVV","pinned":false,"hidden":false,"mode":"md"},{"id":579,"value":"print_insts(`\nvfadd.vv\nvfredsum.vs\nvfsub.vv\nvfredosum.vs\nvfmin.vv\nvfredmin.vs\nvfmax.vv\nvfredmax.vs\nvfsgnj.vv\nvfsgnjn.vv\nvfsgnjx.vv\nvfmv.f.s\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":583,"value":"print_insts(`\nvmfeq.vv\nvmfle.vv\nvmflt.vv\nvmfne.vv\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":587,"value":"print_insts(Object.keys(opcodesAll.rvv).filter(e => e.match(/vf[wn]*cvt./)))","pinned":false,"hidden":false,"mode":"ojs"},{"id":591,"value":"print_insts(`\nvfsqrt.v\nvfrsqrt7.v\nvfrec7.v\nvfclass.v\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":595,"value":"OPIVX","pinned":false,"hidden":false,"mode":"md"},{"id":600,"value":"print_insts(`\nvadc.vxm\nvmadc.vxm\nvsbc.vxm\nvmsbc.vxm\nvmerge.vxm\nvmv.v.x\nvmseq.vx\nvmsne.vx\nvmsltu.vx\nvmslt.vx\nvmsleu.vx\nvmsle.vx\nvmsgtu.vx\nvmsgt.vx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":604,"value":"print_insts(`\nvadc.vxm\nvmadc.vxm\nvsbc.vxm\nvmsbc.vxm\nvmerge.vxm\nvmv.v.x\nvmseq.vx\nvmsne.vx\nvmsltu.vx\nvmslt.vx\nvmsleu.vx\nvmsle.vx\nvmsgtu.vx\nvmsgt.vx\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":5,"value":"import { extract, opcodesAll, print_insts, isaTable, tabler } from '@drom/riscv-opcodes'","pinned":false,"hidden":false,"mode":"ojs"},{"id":1080,"value":"tabler32 = tabler(32)","pinned":false,"hidden":false,"mode":"ojs"}],"files":"$W32","stdlib":"1","titling":"auto"}