30:T9c6,classify = n => { if (n.name.match(/v((macc|nmsac|madd|nmsub|wmaccu|wmacc|wmaccsu)|f(w)?(n)?m(acc|sac|add|sub)).vv/)) return 'opfvvacc'; if (n.name.match(/v((macc|nmsac|madd|nmsub|wmaccu|wmacc|wmaccsu|wmaccus)|f(w)?(n)?m(acc|sac|add|sub)).v(f|x)/)) return 'opfvfacc'; if (n.name.match(/vmv(\d)r.v/)) return 'opivi'; if (n.name.match(/vid.v/)) return 'opivv'; if (n.name.match(/vmv.x.s/)) return 'opivvrd'; if (n.name.match(/vmv.v.x|vfmv.s.f|vfmv.v.f|vfmerge.vfm|vmv.s.x/)) return 'opfvf'; if ('wd'.split(/\s+/).every(e => n.args.includes(e))) return 'vamo'; if (n.opcodes['1..0'] === 0) return 'cl'; if (n.name.match(/vle(\d+).v/)) return 'vle'; if (n.name.match(/vse(\d+).v/)) return 'vse'; if (n.name.match(/vluxei(\d+).v/)) return 'vluxei'; if (n.name.match(/vsuxei(\d+).v/)) return 'vsuxei'; if (n.name.match(/vlse(\d+).v/)) return 'vlse'; if (n.name.match(/vsse(\d+).v/)) return 'vsse'; if (n.name.match(/vloxei(\d+).v/)) return 'vluxei'; if (n.name.match(/vsoxei(\d+).v/)) return 'vsuxei'; if (n.name.match(/vl(\d+)re(\d+).v/)) return 'vle'; if (n.name.match(/vs(\d+)r.v/)) return 'vse'; if (n.name.match(/vfmv.f.s|vmv.v.v|(.vvm$)/)) return 'opfvv'; if ( 'simm5'.split(/\s+/).every(e => n.args.includes(e))) return 'opivi'; if ('vm vs2 rs1 vd'.split(/\s+/).every(e => n.args.includes(e))) return 'opfvf'; if ('vm vs2 vs1 vd'.split(/\s+/).every(e => n.args.includes(e))) return 'opfvv'; if ('vm vs2 vd'.split(/\s+/).every(e => n.args.includes(e))) return 'opfvv'; if ('vm rs1 vd'.split(/\s+/).every(e => n.args.includes(e))) return 'vle'; if ( 'vs2 rs1 vd'.split(/\s+/).every(e => n.args.includes(e))) return 'opfvf'; if ( 'vs2 vs1 vd'.split(/\s+/).every(e => n.args.includes(e))) return 'opivv'; if ( 'vm vs2 rd'.split(/\s+/).every(e => n.args.includes(e))) return 'opivvrd'; if (n.name === 'fence' || n.name === 'fence.tso' || n.name === 'pause') return 'fence'; if (n.args.includes('aqrl')) return 'amo'; if (n.args.includes('shamt')) return 'ish'; if (n.args.includes('shamtw')) return 'ishw'; if (n.args.includes('imm20')) return 'u'; if (n.args.includes('jimm20')) return 'uj'; if (n.name.slice(0, 3) === 'csr') return 'csr'; if (n.args.includes('imm12') || n.name === 'ecall' || n.name === 'ebreak') return 'i'; if (n.args.includes('imm12hi')) return 's'; if (n.args.includes('bimm12hi')) return 'sb'; if (n.args.includes('rs3')) return 'r4'; return 'r'; }31:T309c,isaTypes = (obj) => { obj = obj || {}; const opo = obj.opcodes || {}; const args = obj.args || []; const op = opo['1..0'] === undefined ? 'op' : opo['1..0']; const func3 = opo['15..13'] === undefined ? 'func3' : opo['15..13']; const amoop = opo['31..27'] === undefined ? 'amoop' : opo['31..27']; let opcode = (opo['1..0'] + (opo['6..2'] << 2)); if (opo['6..0'] !== undefined) opcode = opo['6..0']; if (Number.isNaN(opcode)) opcode = 'opcode'; const funct2 = opo['26..25'] === undefined ? 'funct2' : opo['26..25']; let funct3 = opo['14..12'] === undefined ? 'funct3' : opo['14..12']; if (args.includes('rm')) funct3 = 'rm'; let funct7 = (opo['26..25'] + (opo['31..27'] << 2)); if (opo['31..25'] !== undefined) funct7 = opo['31..25']; if (Number.isNaN(funct7)) funct7 = 'funct7'; let funct6 = opo['31..26'] === undefined ? 'funct6' : opo['31..26']; let rs2 = opo['24..20']; if (rs2 === undefined) rs2 = 'rs2'; let rs3 = (opo['28..27'] + (opo['31..29'] << 2)); if (Number.isNaN(rs3)) rs3 = 'rs3'; let shamt = opo['24..20']; if (shamt === undefined) shamt = 'shamt'; let shamtw = opo['25..20']; if (shamtw === undefined) shamtw = 'shamt'; let imm20 = opo['31..20']; if (imm20 === undefined) imm20 = 'imm[11:0]'; let simm5 = opo['19..15']; if (simm5 === undefined) simm5 = 'simm5'; let mew = opo['28']; if (mew === undefined) mew = 'mew'; let mop = opo['27..26']; if (mop === undefined) mop = 'mop'; let width = opo['14..12']; if (width === undefined) width = 'width'; let lumop = opo['24..20']; if (lumop === undefined) lumop = 'lumop'; let sumop = opo['24..20']; if (sumop === undefined) sumop = 'sumop'; let vm = opo['25']; if (vm === undefined) vm = 'vm'; let vs1 = opo['19..15']; if (vs1 === undefined) vs1 = 'vs1'; let vs2 = opo['24..20']; if (vs2 === undefined) vs2 = 'vs2'; let nf = opo['31..29']; if (nf === undefined) nf = 'nf'; if (opo['31..28'] !== undefined) { nf = opo['31..28'] >> 1; mew = opo['31..28'] & 1; } return { r: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: rs2, type: (typeof rs2 === 'number') ? undefined : 4}, {bits: 7, name: funct7} ], i: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 12, name: imm20, type: (typeof imm20 === 'number') ? undefined : 3}, ], s: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'imm[4:0]', type: 3}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: rs2, type: (typeof rs2 === 'number') ? undefined : 4}, {bits: 7, name: 'imm[11:5]', type: 3} ], sb: () => [ {bits: 7, name: opcode}, {bits: 1, name: '[11]', type: 3}, {bits: 4, name: 'imm[4:1]', type: 3}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: rs2, type: (typeof rs2 === 'number') ? undefined : 4}, {bits: 6, name: 'imm[10:5]', type: 3}, {bits: 1, name: '[12]', type: 3} ], u: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 20, name: 'imm[31:12]', type: 3} ], uj: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 8, name: 'imm[19:12]', type: 3}, {bits: 1, name: '[11]', type: 3}, {bits: 10, name: 'imm[10:1]', type: 3}, {bits: 1, name: '[20]', type: 3} ], a: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 8, name: 'imm[19:12]', type: 3}, {bits: 1, name: '[11]', type: 3}, {bits: 10, name: 'imm[10:1]', type: 3}, {bits: 1, name: '[20]', type: 3} ], r4: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: rs2, type: (typeof rs2 === 'number') ? undefined : 4}, {bits: 2, name: funct2}, {bits: 5, name: rs3, type: (typeof rs3 === 'number') ? undefined : 4}, ], ish: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: shamt, type: (typeof shamt === 'number') ? undefined : 3}, {bits: 1}, {bits: 6, name: funct6} ], ishw: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: shamtw, type: (typeof shamtw === 'number') ? undefined : 3}, {bits: 7, name: funct7} ], fence: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 4, name: 'succ'}, {bits: 4, name: 'pred'}, {bits: 4, name: 'fm'}, ], amo: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: rs2, type: (typeof rs2 === 'number') ? undefined : 4}, {bits: 1, name: 'rl'}, {bits: 1, name: 'aq'}, {bits: 5, name: rs3}, ], csr: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: 'rs1', type: 4}, {bits: 12, name: imm20, type: (typeof imm20 === 'number') ? undefined : 3}, ], vle: () => [ // Vector Unit-Stride Instructions (including segment part) {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: width}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: lumop}, {bits: 1, name: vm}, {bits: 2, name: mop}, {bits: 1, name: mew}, {bits: 3, name: nf}, ], vse: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vs3', type: 4}, {bits: 3, name: width}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: sumop}, {bits: 1, name: vm}, {bits: 2, name: mop}, {bits: 1, name: mew}, {bits: 3, name: nf}, ], vluxei: () => [ // Vector Indexed-Unordered Instructions (including segment part) {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: width}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 2, name: mop}, {bits: 1, name: mew}, {bits: 3, name: nf}, ], vsuxei: () => [ // VSX* indexed {bits: 7, name: opcode}, {bits: 5, name: 'vs3', type: 4}, {bits: 3, name: width}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 2, name: mop}, {bits: 1, name: mew}, {bits: 3, name: nf}, ], vlse: () => [ // Vector Strided Instructions (including segment part) {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: width}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'rs2', type: 4}, {bits: 1, name: vm}, {bits: 2, name: mop}, {bits: 1, name: mew}, {bits: 3, name: nf}, ], vsse: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vs3', type: 4}, {bits: 3, name: width}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'rs2', type: 4}, {bits: 1, name: vm}, {bits: 2, name: mop}, {bits: 1, name: mew}, {bits: 3, name: nf}, ], opfvf: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: 5}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 6, name: funct6}, ], opfvfacc: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vd / vs3', type: 7}, {bits: 3, name: 5}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 6, name: funct6}, ], opfvv: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: vs1, type: (typeof vs1 === 'number') ? undefined : 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 6, name: funct6}, ], opfvvacc: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vd / vs3', type: 7}, {bits: 3, name: funct3}, {bits: 5, name: vs1, type: (typeof vs1 === 'number') ? undefined : 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 6, name: funct6}, ], opivv: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: vs1, type: (typeof vs1 === 'number') ? undefined : 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 6, name: funct6}, ], opivi: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: simm5, type: (typeof simm5 === 'number') ? undefined : 3}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 6, name: funct6}, ], opivvrd: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'rd', type: 2}, {bits: 3, name: funct3}, {bits: 5, name: vs1, type: (typeof vs1 === 'number') ? undefined : 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 6, name: funct6}, ], vamo: () => [ {bits: 7, name: opcode}, {bits: 5, name: 'vd', type: 2}, {bits: 3, name: width}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: vs2, type: (typeof vs2 === 'number') ? undefined : 4}, {bits: 1, name: vm}, {bits: 1, name: 'wd'}, {bits: 5, name: amoop}, ], cr: () => [ {bits: 2, name: op}, {bits: 5, name: 'rs2', type: 4}, {bits: 5, name: 'rd / rs1', type: 7}, {bits: 4, name: 'funct4', type: 8}, ], ci: () => [ {bits: 2, name: op}, {bits: 5, name: 'imm', type: 3}, {bits: 5, name: 'rd / rs1', type: 7}, {bits: 1, name: 'imm', type: 3}, {bits: 3, name: func3, type: 8}, ], css: () => [ {bits: 2, name: op}, {bits: 5, name: 'rs2', type: 4}, {bits: 6, name: 'imm', type: 3}, {bits: 3, name: func3, type: 8}, ], ciw: () => [ {bits: 2, name: op}, {bits: 3, name: 'rd`', type: 2}, {bits: 8, name: 'imm', type: 3}, {bits: 3, name: func3, type: 8}, ], cl: () => [ {bits: 2, name: op}, {bits: 3, name: 'rd`', type: 2}, {bits: 2, name: 'imm', type: 3}, {bits: 3, name: 'rs1`', type: 4}, {bits: 3, name: 'imm', type: 3}, {bits: 3, name: func3, type: 8}, ], cs: () => [ {bits: 2, name: op}, {bits: 3, name: 'rs2`', type: 4}, {bits: 2, name: 'imm', type: 3}, {bits: 3, name: 'rs1`', type: 4}, {bits: 3, name: 'imm', type: 3}, {bits: 3, name: func3, type: 8}, ], ca: () => [ {bits: 2, name: op}, {bits: 3, name: 'rs2`', type: 4}, {bits: 2, name: 'funct2', type: 8}, {bits: 3, name: 'rd` / rs1`', type: 7}, {bits: 6, name: 'funct6', type: 8}, ], cb: () => [ {bits: 2, name: op}, {bits: 5, name: 'offset', type: 3}, {bits: 3, name: 'rd` / rs1`', type: 7}, {bits: 3, name: 'offset', type: 3}, {bits: 3, name: func3, type: 8}, ], cj: () => [ {bits: 2, name: op}, {bits: 11, name: 'jump target', type: 3}, {bits: 3, name: func3, type: 8}, ] }; } 32:[] 2e:{"title":"RISC-V OPCODES","cells":[{"id":195,"value":"# RISC-V OPCODES","pinned":false,"hidden":false,"mode":"md"},{"id":177,"value":"ALL_REAL_ILEN32_OPCODES = 'rv32_i rv64_i rv32_m rv64_m rv32_a rv64_a rv32_h rv64_h rv32_f rv64_f rv32_d rv64_d rv32_q rv64_q rv32_b rv64_b system rv32zfh rv32d-zfh rv32q-zfh rv64zfh rvk rv32k rv64k'.split(/\\s+/)","pinned":false,"hidden":false,"mode":"ojs"},{"id":185,"value":"ALL_REAL_OPCODES = ALL_REAL_ILEN32_OPCODES.concat('rvc rv32c rv64c custom rvv'.split(/\\s+/))","pinned":false,"hidden":false,"mode":"ojs"},{"id":188,"value":"ALL_OPCODES = ['pseudo', ...ALL_REAL_OPCODES, 'rvv-pseudo']","pinned":false,"hidden":false,"mode":"ojs"},{"id":23,"value":"opcodesAll = extract(ALL_OPCODES)","pinned":false,"hidden":false,"mode":"ojs"},{"id":357,"value":"opcodesAllFlat = Object.keys(opcodesAll).reduce((res, key) => Object.assign(res, opcodesAll[key]), {})","pinned":false,"hidden":false,"mode":"ojs"},{"id":208,"value":"print_header('r i s sb u uj')","pinned":false,"hidden":false,"mode":"ojs"},{"id":223,"value":"### RV32I Base Instruction Set","pinned":false,"hidden":false,"mode":"md"},{"id":211,"value":"print_insts(`\nlui auipc\njal jalr beq bne blt bge bltu bgeu\nlb lh lw lbu lhu sb sh sw\naddi slti sltiu xori ori andi\nslli srli srai\nadd sub sll slt sltu xor srl sra or and\nfence\necall ebreak\n`)\n/*\n\n pause\n fence.tso\n\n*/","pinned":false,"hidden":false,"mode":"ojs"},{"id":228,"value":"print_header('r i s')","pinned":false,"hidden":false,"mode":"ojs"},{"id":231,"value":"### RV64I Base Instruction Set (in addition to RV32I)","pinned":false,"hidden":false,"mode":"md"},{"id":236,"value":"print_insts(`\nlwu ld sd\nslli srli srai\naddiw slliw srliw sraiw\naddw subw sllw srlw sraw\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":239,"value":"### RV32/RV64 *Zifencei* Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":243,"value":"print_insts('fence.i')","pinned":false,"hidden":false,"mode":"ojs"},{"id":246,"value":"### RV32/RV64 *Zicsr* Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":250,"value":"print_insts(`\ncsrrw csrrs csrrc\ncsrrwi csrrsi csrrci\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":253,"value":"### RV32M Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":259,"value":"print_insts(`\nmul mulh mulhsu mulhu\ndiv divu rem remu\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":264,"value":"### RV64M Standard Extension (in addition to RV32M)","pinned":false,"hidden":false,"mode":"md"},{"id":268,"value":"print_insts('mulw divw divuw remw remuw')","pinned":false,"hidden":false,"mode":"ojs"},{"id":271,"value":"print_header('r')","pinned":false,"hidden":false,"mode":"ojs"},{"id":274,"value":"### RV32A Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":278,"value":"print_insts(`\nlr.w sc.w\namoswap.w\namoadd.w amoxor.w amoand.w amoor.w\namomin.w amomax.w amominu.w amomaxu.w\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":285,"value":"### RV64A Standard Extension (in addition to RV32A)","pinned":false,"hidden":false,"mode":"md"},{"id":289,"value":"print_insts(`\nlr.d sc.d\namoswap.d\namoadd.d amoxor.d amoand.d amoor.d\namomin.d amomax.d amominu.d amomaxu.d\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":292,"value":"print_header('r r4 i s')","pinned":false,"hidden":false,"mode":"ojs"},{"id":295,"value":"### RV32F Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":298,"value":"print_insts(`\nflw fsw\nfmadd.s fmsub.s fnmsub.s fnmadd.s\nfadd.s fsub.s fmul.s fdiv.s fsqrt.s\nfsgnj.s fsgnjn.s fsgnjx.s fmin.s fmax.s\nfcvt.w.s fcvt.wu.s fmv.x.w\nfeq.s flt.s fle.s fclass.s\nfcvt.s.w fcvt.s.wu fmv.w.x\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":302,"value":"### RV64F Standard Extension (in addition to RV32F)","pinned":false,"hidden":false,"mode":"md"},{"id":306,"value":"print_insts(`\nfcvt.l.s fcvt.lu.s\nfcvt.s.l fcvt.s.lu\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":325,"value":"print_header('r r4 i s')","pinned":false,"hidden":false,"mode":"ojs"},{"id":309,"value":"### RV32D Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":331,"value":"print_insts(`\nfld fsd\nfmadd.d fmsub.d fnmsub.d fnmadd.d\nfadd.d fsub.d fmul.d fdiv.d fsqrt.d\nfsgnj.d fsgnjn.d fsgnjx.d fmin.d fmax.d\nfcvt.s.d fcvt.d.s\nfeq.d flt.d fle.d fclass.d\nfcvt.w.d fcvt.wu.d\nfcvt.d.w fcvt.d.wu\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":313,"value":"### RV64D Standard Extension (in addition to RV32D)","pinned":false,"hidden":false,"mode":"md"},{"id":334,"value":"print_insts(`\nfcvt.l.d fcvt.lu.d fmv.x.d\nfcvt.d.l fcvt.d.lu fmv.d.x\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":328,"value":"print_header('r r4 i s')","pinned":false,"hidden":false,"mode":"ojs"},{"id":317,"value":"### RV32Q Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":337,"value":"print_insts(`\nflq fsq\nfmadd.q fmsub.q fnmsub.q fnmadd.q\nfadd.q fsub.q fmul.q fdiv.q fsqrt.q\nfsgnj.q fsgnjn.q fsgnjx.q fmin.q fmax.q\nfcvt.s.q fcvt.q.s\nfcvt.d.q fcvt.q.d\nfeq.q flt.q fle.q fclass.q\nfcvt.w.q fcvt.wu.q\nfcvt.q.w fcvt.q.wu\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":321,"value":"### RV64Q Standard Extension (in addition to RV32Q)","pinned":false,"hidden":false,"mode":"md"},{"id":344,"value":"print_insts(`\nfcvt.l.q fcvt.lu.q\nfcvt.q.l fcvt.q.lu\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":1153,"value":"### RV32Zfh Standard Extension","pinned":false,"hidden":false,"mode":"md"},{"id":1151,"value":"print_insts(`\nflh fsh\n\nfmadd.h fmsub.h fnmadd.h fnmsub.h fadd.h fsub.h\n\nfmul.h fdiv.h fsqrt.h fsgnj.h fsgnjn.h fsgnjx.h\nfmin.h fmax.h\n\nfcvt.s.h fcvt.d.h fcvt.q.h\nfcvt.h.s fcvt.h.d fcvt.h.q\n\nfmv.x.h\n\nfeq.h flt.h fle.h fclass.h\n\nfcvt.w.h fcvt.wu.h\nfcvt.h.w fcvt.h.wu\n\nfmv.h.x\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":1190,"value":"### RV64Zfh Standard Extension (in addition to RV32Zfh)","pinned":false,"hidden":false,"mode":"md"},{"id":1195,"value":"print_insts(`\nfcvt.l.h fcvt.lu.h\nfcvt.h.l fcvt.h.lu\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":16,"value":"## Appendix","pinned":false,"hidden":false,"mode":"md"},{"id":155,"value":"arglut = ({\nrd: [11,7],\nrt: [19,15], // source+dest register address. Overlaps rs1.\nrs1: [19,15],\nrs2: [24,20],\nrs3: [31,27],\naqrl: [26,25],\nfm: [31,28],\npred: [27,24],\nsucc: [23,20],\nrm: [14,12],\nfunct3: [14,12],\nimm20: [31,12],\njimm20: [31,12],\nimm12: [31,20],\nimm12hi: [31,25],\nbimm12hi: [31,25],\nimm12lo: [11,7],\nbimm12lo: [11,7],\nzimm: [19,15],\nshamt: [25,20],\nshamtw: [24,20],\nbs: [31,30], // byte select for RV32K AES\nrnum: [23,20], // round constant for RV64 AES\n// for vectors\nvd: [11,7],\nvs3: [11,7],\nvs1: [19,15],\nvs2: [24,20],\nvm: [25,25],\nwd: [26,26],\namoop: [31,27],\nnf: [31,29],\nsimm5: [19,15],\nzimm10: [29,20],\nzimm11: [30,20],\n})","pinned":false,"hidden":false,"mode":"ojs"},{"id":372,"value":"$30","pinned":false,"hidden":false,"mode":"ojs"},{"id":82,"value":"op2obj = txt => {\n const t1 = txt.split(/\\n/);\n const t2 = t1.reduce((res, row) => {\n row = row.trim();\n if (row === '') return res;\n if (row.slice(0, 1) === '#') return res;\n const els = row.split(/\\s+/);\n const name = els.shift();\n const args = [];\n const opcodes1 = [];\n els.map(e => ((e in arglut) ? args : opcodes1).push(e));\n const opcodes = opcodes1.reduce((res, e) => {\n const ee = e.split('=');\n res[ee[0]] = Number(ee[1]);\n return res;\n }, {});\n const instr = {name, args, opcodes};\n instr.type = classify(instr);\n res[name] = instr;\n return res;\n }, {});\n return t2;\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":20,"value":"extract = async names => {\n if (typeof names === 'string') {\n names = names.split(/\\s+/);\n }\n const requests = names.map(name => fetch('https://raw.githubusercontent.com/riscv/riscv-opcodes/master/' + name));\n const responses = await Promise.all(requests);\n const texts = await Promise.all(responses.map(r => r.text()));\n const res = {};\n names.map((name, idx) => {\n res[name] = op2obj(texts[idx], name);\n })\n return res;\n} ","pinned":false,"hidden":false,"mode":"ojs"},{"id":467,"value":"$31","pinned":false,"hidden":false,"mode":"ojs"},{"id":1136,"value":"tabler = ilen => function () {\n let labels = [];\n let fields = [];\n for (const fn of arguments) {\n fn(labels, fields);\n }\n const lanes = labels.length;\n return isaTable(fields, {\n hflip: true,\n hspace: width,\n bits: lanes * ilen, lanes,\n compact: true,\n margin: {right: width / 6},\n label: {right: labels}\n }); \n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":401,"value":"isaTable = (desc, opt) => {\n const div = document.createElement('div');\n const render = onml.renderer(div);\n const ml = bitField.render(desc, opt);\n render(ml);\n return div;\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":204,"value":"print_header = names => {\n if (typeof names === 'string') {\n names = names.split(/\\s+/);\n }\n const fields = [];\n const labels = [];\n let lanes = 0;\n \n names.map(name => {\n lanes += 1;\n fields.push(...isaTypes()[name]());\n labels.push(name.toUpperCase() + '-type');\n });\n return isaTable(fields, {\n hflip: true,\n hspace: width,\n bits: lanes * 32, lanes,\n compact: true,\n margin: {right: width / 6},\n label: {right: labels}\n });\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":213,"value":"print_insts = names => {\n if (typeof names === 'string') {\n names = names.trim().split(/\\s+/);\n }\n const fields = [];\n const labels = [];\n let lanes = 0; \n names.map(name => {\n const ns = name.split('/');\n \n const opcode = (ns.length === 1)\n ? opcodesAllFlat[name]\n : opcodesAll[ns[1]][ns[0]];\n \n lanes += 1;\n fields.push(...isaTypes(opcode)[opcode.type]());\n labels.push(ns[0].toUpperCase());\n });\n return isaTable(fields, {\n hflip: true,\n hspace: width,\n bits: lanes * 32, lanes,\n compact: true,\n margin: {right: width / 6},\n label: {right: labels}\n });\n\n return names;\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":912,"value":"print_insts_16 = names => {\n if (typeof names === 'string') {\n names = names.trim().split(/\\s+/);\n }\n const fields = [];\n const labels = [];\n let lanes = 0; \n names.map(name => {\n const ns = name.split('/');\n \n const opcode = (ns.length === 1)\n ? opcodesAllFlat[name]\n : opcodesAll[ns[1]][ns[0]];\n \n lanes += 1;\n fields.push(...isaTypes(opcode)[opcode.type]());\n labels.push(ns[0].toUpperCase());\n });\n return isaTable(fields, {\n hflip: true,\n hspace: width,\n bits: lanes * 16, lanes,\n compact: true,\n margin: {right: width / 6},\n label: {right: labels}\n });\n\n return names;\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":394,"value":"tspan = require('tspan')","pinned":false,"hidden":false,"mode":"ojs"},{"id":398,"value":"onml = require('onml')","pinned":false,"hidden":false,"mode":"ojs"},{"id":459,"value":"bitField = require('bit-field@1.5.2')","pinned":false,"hidden":false,"mode":"ojs"}],"files":"$W32","stdlib":"1","titling":"auto"}