30:[] 2e:{"title":"Scan bus definition","cells":[{"id":0,"value":"md`\n# Scan bus definition\n\nsifive.com/TEST/SCAN_INSERTION/0.1.0\n\nhttps://github.com/sifive/duh-bus/pull/21\n\n|name|dir|width|required|description|\n|-|-|-|-|\n| CLOCK | input | 1 | yes | scan clock port for DFFs\n| RESET | input | 1 | - | async reset for DFFs\n| TEST_MODE | input | N | - | enable scan mode\n| CLOCK_EN | input | 1 | - | clock enable\n| SE | input | 1 | - | scan enable\n| SI | input | N | - | scan chain input\n| SO | output | N | - | scan chain outputs\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":111,"value":"md`\n\n### Case 1\n\nComponent with single clock, async reset.\n\n\\`\\`\\`js\n{\n CLOCK: 'clk'\n RESET: '~reset_n'\n}\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":81,"value":"render(`\nmodule dut(\n input clk, reset_n,\n output out\n);\n\nalways @(posedge clk or negedge reset_n) if (~reset_n) out <= 0; else out <= inp;\n\nendmodule\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":114,"value":"md`\n\n### Case 2\n\nComponent with reset synchronizer.\n\n\\`\\`\\`js\n[{\n CLOCK: 'clk',\n RESET: '~reset_n'\n},{\n CLOCK: 'clk',\n RESET: '~test_reset_n'\n TEST_MODE: 'test_mode'\n}]\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":18,"value":"render(`\nmodule dut(\n input clk, reset_n, test_mode, test_reset_n,\n // input inp,\n output out\n);\n\nreg f0, f1, f2;\n\nalways @(posedge clk or negedge reset_n) if (~reset_n) f0 <= 0; else f0 <= 1;\nalways @(posedge clk or negedge reset_n) if (~reset_n) f1 <= 0; else f1 <= f0;\n\nassign rstn = test_mode ? test_reset_n : f1;\n\nalways @(posedge clk or negedge rstn) if (~rstn) f2 <= 0; else f2 <= inp;\n\nassign out = f2;\n\nendmodule\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":117,"value":"md`\n\n### Case 3\n\nComponent with clock MUX\n\n\\`\\`\\`js\n{\n CLOCK: 'clk1',\n RESET: '~async_reset_n',\n TEST_MODE: 'tmode'\n}\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":97,"value":"render(`\nmodule dut(\n input clk1, clk2, pll, async_reset_n, tmode,\n input clk_sel, clk_sel2,\n // input inp,\n output out\n);\n\nwire clk;\n\nassign clk = (clk_sel | tmode) ? clk1 : (clk_sel2 ? clk2 : pll);\n\nalways @(posedge clk or negedge async_reset_n) if (~async_reset_n) out <= 0; else out <= inp;\n\nendmodule\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":192,"value":"md`\n\n### Case 4\n\nComponent with clock enable\n\n\\`\\`\\`js\n{\n CLOCK: 'clk',\n RESETn: 'async_reset_n',\n CLOCK_EN: 'clk_en'\n}\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":185,"value":"render(`\nmodule dut(\n input clk, clk_en, async_reset_n,\n // input inp,\n output out\n);\n\nwire clk0; assign clk0 = clk & clk_en;\n\nalways @(posedge clk0 or negedge async_reset_n) if (~async_reset_n) out <= 0; else out <= inp;\n\nendmodule\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":206,"value":"md`\n### Case 5\n\nComponent with clock MUX and clock Enable\n\n\\`\\`\\`js\n{\n CLOCK: 'clk1',\n CLOCK_EN: 'clk1_en',\n RESET: 'async_reset',\n TEST_MODE: 'tmode'\n}\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":199,"value":"render(`\nmodule dut(\n input clk1, clk1_en, clk2, pll, async_reset, tmode,\n input clk_sel, clk_sel2,\n // input inp,\n output out\n);\n\nwire clk;\nwire clk1_;\nassign clk1_ = clk1 & clk1_en;\n\nassign clk = (clk_sel | tmode) ? clk1_ : (clk_sel2 ? clk2 : pll);\n\nalways @(posedge clk or posedge async_reset) if (async_reset) out <= 0; else out <= inp;\n\nendmodule\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":217,"value":"md`\n### Case 6\n\nComponent with clock MUX and clock Enable on the scan clock path\n\n\\`\\`\\`js\n{\n CLOCK: 'clk1',\n CLOCK_EN: 'clk_any_en',\n RESET: 'async_reset',\n TEST_MODE: ['~func_mode[7]', 'func_mode[6:0]']\n}\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":210,"value":"render(`\nmodule dut(\n input clk1, clk_any_en, clk2, pll, async_reset,\n input [7:0] func_mode,\n input clk_sel, clk_sel2,\n // input inp,\n output out\n);\n\nwire clk;\n\nassign clk = ((clk_sel | (~func_mode[7] & &func_mode[6:0])) ? clk1 : (clk_sel2 ? clk2 : pll)) & clk_any_en;\n\nalways @(posedge clk or posedge async_reset) if (async_reset) out <= 0; else out <= inp;\n\nendmodule\n`)","pinned":false,"hidden":false,"mode":"ojs"},{"id":279,"value":"md`\n### Case 7\n\nComponent inserted scan chains\n\n\\`\\`\\`js\n{\n CLOCK: 'clk1',\n RESET: 'arst',\n TEST_MODE: 'scan_mode',\n SE: 'SE',\n SI: ['test_si'], // port width 500\n SO: ['test_so[0]', 'test_so[1]', ..., 'test_si[499]'], // sliced & concatenated\n}\n\\`\\`\\`\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":5,"value":"md`\n## Appendix\n`","pinned":false,"hidden":false,"mode":"ojs"},{"id":9,"value":"netlistsvg = {\n var ELK = await require('https://nturley.github.io/netlistsvg/elk.bundled.js')\n window.ELK = ELK\n return require('https://nturley.github.io/netlistsvg/built/netlistsvg.bundle.js')\n}","pinned":false,"hidden":false,"mode":"ojs"},{"id":12,"value":"YosysJS = require('https://nturley.github.io/yosysjs.js').catch(() => window.YosysJS)","pinned":false,"hidden":false,"mode":"ojs"},{"id":15,"value":"ys = new Promise(function(accept, reject) { YosysJS.create(\"\", accept) })","pinned":false,"hidden":false,"mode":"ojs"},{"id":69,"value":"render = async src => html`${await netlistsvg.render(netlistsvg.digitalSkin, (src => {\n ys.write_file('input.v', src)\n ys.run('design -reset; read_verilog input.v; proc; opt_clean; write_json output.json')\n return JSON.parse(ys.read_file('output.json'))\n})(src))}`","pinned":false,"hidden":false,"mode":"ojs"}],"files":"$W30","stdlib":"1","titling":"auto"}